• Disclaimer: This Vendor's Forum is a paid-for commercial area. Unlike the rest of diyAudio, the Vendor has complete control of what may or may not be posted in this forum. If you wish to discuss technical matters outside the bounds of what is permitted by the Vendor, please use the non-commercial areas of diyAudio to do so.

Buffalo III - SE

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Jump to Latest
Russ White

Russ White

Member
Joined 2005
twistedpearaudio.com
You could use the already available Buffalo 3 for 8 channel applications if you like.

We are working (actually have been for quite a while) on the Buffalo 4.0 but we won't be releasing any details until we are closer to real production, but I can confirm that the same board will work in any combination of channels supported by the chip from 1 to 8. The board is a completely new design to get the most out of the new chip - but will be stacking compatible with IVY-III and Legato.

The new chips are not in production from ESS yet (good thing because the prototype chips have some errors) - but we are prototyping which is the best we can do right now. :)

Cheers!
Russ
 
Last edited:
dahlberg

dahlberg

Member
Joined 2005
dahlbergaudiodesign.com
Russ White said:
You could use the already available Buffalo 3 for 8 channel applications if you like.

We are working (actually have been for quite a while) on the Buffalo 4.0 but we won't be releasing any details until we are closer to real production, but I can confirm that the same board will work in any combination of channels supported by the chip from 1 to 8. The board is a completely new design to get the most out of the new chip - but will be stacking compatible with IVY-III and Legato.

The new chips are not in production from ESS yet (good thing because the prototype chips have some errors) - but we are prototyping which is the best we can do right now. :)

Cheers!
Russ
Click to expand...

Thanks for the fast reply :)
All this is good news for me so I will be waiting for the coming generation, thanks.
 
C

Crom

Member
Joined 2012
I'm trying to resolve a problem with being unable to achieve any lock above 96k and running through the obvious stuff first.

I understand that it's important to keep the Data/LRCK/SCK I2S cables as short as possible and of equal length but does this also include the MCLK cable if I am running synchronously?

ie should all 4 u.fl cables be the same length?

Thanks.
 
C

Crom

Member
Joined 2012
Russ White said:
I will need a lot more data to help you out. :)
Click to expand...

Thanks for jumping on this Russ, it's driving me mad.

Russ White said:
What master clock frequency(s)
Click to expand...
MCLK is being generated by Ian's FIFO clock board. The frequency is automatically switched from 44.1K to 384K depending upon the input I2S stream. There are various indicator LEDS on the board and these are displaying correctly according to input (everything up to 384k).

Russ White said:
What source?
Click to expand...

My regular sources are a pimped up PC and a microrendu. I have also tried a couple of laptops to try to narrow down the problem. I've also tried a few alternative USB > I2s cards (waveio, diyinhk, sonore). The problem is exhibited with all these different sources.

Russ White said:
What firmware?
Click to expand...

No idea which firmware version but the 2 x DAC boards were bought from you 3 years ago (I guess!). I spotted your updated firmware chip as I was researching this. I ordered a new chip late last week and I'll let you know results here.

Hope this helps ;-)
Crom
 
C

Crom

Member
Joined 2012
Yes, I am trying to run sync mode. Yes, DPLL is set to highest (i've read your "freewheeling" comments elsewhere). Firmware's on order so let's see what happens.

Just returning to my original question: I understand that it's important to keep Data/LRCK/SCK I2S cables as short as possible and of equal length but does this also include the MCLK cable...

ie should MCLK be same length as others?

Whilst I'm waiting for the firmware, should I be looking at any other potential issues? In the past I've managed reasonably stable sync-lock as high as 192k - even at 32-bit - but for some reason it is eluding me over the last few months.

Thanks for your help,
Crom
 
B

barrows

Member
Joined 2010
hi

Crom said:
Yes, I am trying to run sync mode. Yes, DPLL is set to highest (i've read your "freewheeling" comments elsewhere). Firmware's on order so let's see what happens.

Just returning to my original question: I understand that it's important to keep Data/LRCK/SCK I2S cables as short as possible and of equal length but does this also include the MCLK cable...

ie should MCLK be same length as others?

Whilst I'm waiting for the firmware, should I be looking at any other potential issues? In the past I've managed reasonably stable sync-lock as high as 192k - even at 32-bit - but for some reason it is eluding me over the last few months.

Thanks for your help,
Crom
Click to expand...

Crom: I have no problem running sync mode direct from the Sonore USB interface direct to a B-IIIse using the masterclock generated by the Sonore board (it was designed for this). I doubt you will have advantage using Ian's FIFO re-clocking board if using the Sonore USB interface, as the Sonore board already re-clocks the signal via Crystek CCHD-957 oscillators on the isolated side of the USB board. The I2S connections in my setup are u.fl with the masterclock cable being longer as well, so no problem with slightly different length cables. This works fine for me up to 384 PCM and DSD 128.
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Top Bottom