A second stage with both emitter follower and cascode is prone to local instability, which is indicated by the 50 MHz peak you see. Some randomly placed RC networks may, at least in simulation, mitigate the effect. But a far more powerful technique, used extensively in IC opamps but apparently mostly unknown to audio designers, is the use of a feed-forward capacitor at the emitter follower. For the schematic you posted in the other thread this would mean a capacitor (roughly 100 pF) from the base of Q19 (Q20) to the base of Q21 (Q22).
Also the capacitors from the current mirror inputs (C5 and C6) to ground look dubious to my eyes. Any reason for these? Also I'm not sure if it is a smart idea to implemented the amp without output stage; the second stage output node might be rather sensitive to capacitive loading. Use a small-signal class A emitter follower for prototyping.
Samuel
Also the capacitors from the current mirror inputs (C5 and C6) to ground look dubious to my eyes. Any reason for these? Also I'm not sure if it is a smart idea to implemented the amp without output stage; the second stage output node might be rather sensitive to capacitive loading. Use a small-signal class A emitter follower for prototyping.
Samuel
RC
Hi there,
First of all, I am happy to see Edmond is back on the forum since most of my actual schematic has been discussed with him.
As for the utility of the RC network in simulation it seems indeed rather of lower effect. Or effect in a less important portion of the graphs. However I built once one of those circuits. And also getting back to Samuels comment it indeed helps to lower / annulate oscillations which are like bursts on the scope. I can only guess it is indeed a local oscillation. What I can say for sure is that they have quite effect in reality.
As for the caps to ground in the IPS their effect is indeed very small in simulation and also in my previous pcb, they didn't have any noticeable effect. But I guess they are only useful in case of instability resulting from complex parameters and that in my case they were not needed.
I have a small OPS which is not implemented in this schematic nor in the pcb. I can connect it to the test pcb. I need however a jumper set in the pcb to make it easy. Or I can include the whole stuff on the pcb itself. Mmm I had troubles getting everything fitted on a 100x140mm pcb ... maybe I need to remove fuses and lower rail cap sizes ... it is a prototype anyway and will always be used with a bench powersupply (limited current).
I will check out what your solution brings in the simulation : 100pF between bases of Q19 & Q21 respectively Q20 & Q22
Cheers,
Olivier
Hi there,
First of all, I am happy to see Edmond is back on the forum since most of my actual schematic has been discussed with him.
As for the utility of the RC network in simulation it seems indeed rather of lower effect. Or effect in a less important portion of the graphs. However I built once one of those circuits. And also getting back to Samuels comment it indeed helps to lower / annulate oscillations which are like bursts on the scope. I can only guess it is indeed a local oscillation. What I can say for sure is that they have quite effect in reality.
As for the caps to ground in the IPS their effect is indeed very small in simulation and also in my previous pcb, they didn't have any noticeable effect. But I guess they are only useful in case of instability resulting from complex parameters and that in my case they were not needed.
I have a small OPS which is not implemented in this schematic nor in the pcb. I can connect it to the test pcb. I need however a jumper set in the pcb to make it easy. Or I can include the whole stuff on the pcb itself. Mmm I had troubles getting everything fitted on a 100x140mm pcb ... maybe I need to remove fuses and lower rail cap sizes ... it is a prototype anyway and will always be used with a bench powersupply (limited current).
I will check out what your solution brings in the simulation : 100pF between bases of Q19 & Q21 respectively Q20 & Q22
Cheers,
Olivier
Hi Samuel,
Indeed, those feed-forward capacitors are quite effective in suppressing local instability. More recently, by placing caps more or less 'randomly', I discovered this too.
On the other hand, according to Glen Kleinschmidt, a RC network at the input of the VAS serves one more purpose: reducing the susceptibility to HF ingress.
Those caps vastly improve the PSRR at AF/HF. Remember, Cdom is referenced to the supply rails (instead of gnd), hence....
That's what I told him too.
Cheers,
E.
can anybody will send dr. batra's amplifier circuit/pcb especially.
awaiting curiously masood email khan.shahid251@gmail.com
awaiting curiously masood email khan.shahid251@gmail.com
unusable?
At frequencies of interest the effect is virtual zero (at least in this application). Even at 10MHz the OLG is only 0.4dB less. Is that what you call gross enough to make the technique unusable?
Cheers,
E.
At frequencies of interest the effect is virtual zero (at least in this application). Even at 10MHz the OLG is only 0.4dB less. Is that what you call gross enough to make the technique unusable?
Cheers,
E.
a quick estimate is that it rolls of 1/2 of the diff pair current starting at the pole of the C with the mirror input resistance
good practice will have some V gain between the diff pair degen and and the mirror degen to keep mirror noise contribution low
so the pole may be ~2-4x below unity gain - but power amps typically are ran at Av ~20 or more so the added pole will typically be 4x or more higher than the loop gain intercept frequency (all assuming dominant pole Miller comp)
the added phase shift at the intercept frequency would be <10 degrees - so the added psrr compensation C at the mirror input shouldn't cut available bandwidth by much either
it could be an unacceptable cost at lower/unity closed loop gain
good practice will have some V gain between the diff pair degen and and the mirror degen to keep mirror noise contribution low
so the pole may be ~2-4x below unity gain - but power amps typically are ran at Av ~20 or more so the added pole will typically be 4x or more higher than the loop gain intercept frequency (all assuming dominant pole Miller comp)
the added phase shift at the intercept frequency would be <10 degrees - so the added psrr compensation C at the mirror input shouldn't cut available bandwidth by much either
it could be an unacceptable cost at lower/unity closed loop gain
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RC
Hi Samuel,
I replaced the RC network with the 100pF capacitor between bases of the darlington vas transistors. The result is very similar. It eliminates the gain peak @ 50MHz just like the RC network did before.
I am mitigated about implementing both options on the pcb because I am willing to reduce optional tracks as I fear they make opportunities for problems.
Greetz,
Olivier
Hi Samuel,
I replaced the RC network with the 100pF capacitor between bases of the darlington vas transistors. The result is very similar. It eliminates the gain peak @ 50MHz just like the RC network did before.
I am mitigated about implementing both options on the pcb because I am willing to reduce optional tracks as I fear they make opportunities for problems.
Greetz,
Olivier
Were you are RPI at that time? My older brother brought home the schematics for the Citation 12 from RPI some time in the very early 1970s. I also built a clone from them around that time. Perhaps the plans were floating around the EE department at RPI.
Hi Olivier,
It looks to me like you are doing the right thing. Little peaks in the response like that often concern me and, as Edmond suggests below, can be evidence of local loops that are borderline stable. The Miller compensation loop always has to be looked at closely.
Cheers,
Bob
It only seems pointless if you are looking at the wrong loop.
There are more loops, you know!
Hi Edmond,
Its good to see you back!
Cheers,
Bob
Hi Pete,
Yes, I was at RPI from 1966 to 1970, in the Alpha Sigma Phi Fraternity. I built the Citation 12's while I was at Stanford in 1970-71 getting my MSEE. I don't remember where I got the '12 schematics, but it could very well have been from my time at the "Tute".
BTW, ask your brother if he remembers stories on campus about the "Chain Dialer" - I was the guilty party.
Cheers,
Bob
Even Papa ground is ax on that,
http://cygnus.ipal.org/mirror/www.passlabs.com/images/citation.pdf
http://cygnus.ipal.org/mirror/www.passlabs.com/images/citation.pdf
I think my brother started at RPI in 70 or 71 so he might have just missed you. I will ask him about that!
Miller issues
Hi Olivier,
As Bob pointed out: The Miller compensation loop always has to be looked at closely, I strongly advice you to analyse/simulate both options. Besides, I don't see why a few (tiny) optional tracks on the PCB should pose problems.
I'm aware that simulating the gain and phase of the Millers loops (there are two of them!) involves quite some work. Nevertheless, I think it's worth the effort. You will need a gain probe and few big caps and inductors to combine the two Miller loops into a single one (probing only one of them and leaving the other untouched, will yield meaningless results).
Cheers,
E.
Hi Olivier,
As Bob pointed out: The Miller compensation loop always has to be looked at closely, I strongly advice you to analyse/simulate both options. Besides, I don't see why a few (tiny) optional tracks on the PCB should pose problems.
I'm aware that simulating the gain and phase of the Millers loops (there are two of them!) involves quite some work. Nevertheless, I think it's worth the effort. You will need a gain probe and few big caps and inductors to combine the two Miller loops into a single one (probing only one of them and leaving the other untouched, will yield meaningless results).
Cheers,
E.