AC
Hi Davada,
Hm... I hope you are right, since it would mean that my pcb is ok
However, how can I check this out?
Indeed maybe Bob can tell something about it.
However if you are more interested in this problem you can check the thread here :
HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles
Cheers,
Olivier
Hi Davada,
Hm... I hope you are right, since it would mean that my pcb is ok
However, how can I check this out?
Indeed maybe Bob can tell something about it.
However if you are more interested in this problem you can check the thread here :
HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles
Cheers,
Olivier
Hi Olivier,
I apologize for taking so long to get back to you and have temporarily lost track of a couple of issues. I've been preparing for a business trip to ISSCC in San Francisco and trying to finish up a bunch of stuff at work before I go.
Anyway, thanks for supplying the Bode plots and the explanation of how you measured it. Overall, your results look pretty good in correspondence between simulation and measurement up to at least 500 kHz.
What's going on above 1 MHz could be due to a number of things, some in the simulation and some in the real circuit. For example, in simulation, I don't recall what models you are using for the drivers and output transistors in particular. Forgive me if I've asked this before. Those can make a big difference, and manufacturers' models can be optimistic at HF. I also regrettably don't remember the circuit you are using and what type of output stage is being employed. Since you are using MicroCap, I'm guessing you may not be using my transistor models (not that they are the be-all and end-all, and you may not be using those same devices anyway).
BTW, I'm assuming that what you are simulating and what you have built are identical, including the means whereby you are measuring the Bode plot.
Parasitic inductance and bypassing issues can cause some of the funny business you are seeing in the real world, especially in regard to the output stage behavior.
This sort of thing might also be caused by the CMCL circuit, but I would think CMCL-induced anomolies would show up in both simulation and real world if the simulation is an exact version of the real world amplifier implementation and measurement means.
Particularly if the output stage is a Triple, one thing that I like to do is to measure and simulate with the "output" taken from a center tap of the pre-driver or driver emitter bias resistor so as to take the output stage out of the picture. You may want to try this.
Finally, make sure that any output loading of the amplifier, including output networks, is identical in simulation and real-world measurements. Can I assume that the results you showed are with a simple, close-by 8-ohm resistoive load, and that in addition to that you just have a conventional Zobel network loading the output?
Cheers,
Bob
Hi Davada,
Hm... I hope you are right, since it would mean that my pcb is ok
However, how can I check this out?
Indeed maybe Bob can tell something about it.
However if you are more interested in this problem you can check the thread here :
HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles
Cheers,
Olivier
Hi Oliver,
My comment was more of just a heads up. I've had circuits burst into oscillation just from the insertion of a o-scope probe and if one is not aware of this sort of thing we might think it's the circuit that's at fault.
You're working with a circuit that's proven to be one of the most difficult to make stable.
If you haven't read Bob's book yet, I highly recommend that you do. Bob does address a solution for the IPS/VAS bias instability issue with this topology.
David.
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Hi Bob,
For now there is no OPS in the circuit. The Vas output is the output node. My measurements for now are with the VAS unloaded by any resistor or anything else.
The transistors used are all 2SA1381 and 2SC3503 IPS & VAS.
However I would like to ask your specific opinion on one thing about pcb's. Imagine my PCB is 4 layered. Layer 1 Carries most op the power supply and higher voltage nodes, the rest of the layer is connected to a total copper pour in its turn connected to terminal (call it L1T). Layers 2 Is a 95% copper plane, it carries no tracks and it's only broken by the drill holes. The nearly full plane is connected to L2T. Layer 3 Conducts mainly track that are signal ground. This signal ground goes to a terminal Signal Ground. The rest of that layer, like in layer 1 is poured over with copper and led to a terminal L3T. Layer 4 carries other nodes and some tracks, just because layer 1 was cluttered and I didn't like it to run on the ground plane or signal ground plane. The rest of layer 4 is like layer 1 again, open spaces are poured up with copper and connected to a terminal L4T.
The idea was EMI reduction and mainly shielding.
Apart from guessing the best combination of tying L1T,L2T,L3T and L4T together and to what node like, common ground or decoupling ground or a combination again, it came up to me that these massive copper areas connected together and sandwishing tracks etc might provoke severe stray capacitance or parasitic capacitors?
Apart from the price is good to step up to multilayers to be able to have ground planes (if yes, full copper or hatched?) and is it wise to pour copper on the layers in order to fill the empty space with copper in turn connected to some ground. Maybe just pouring but not conected at all?
I will restart my circuit from scratch anyway using the same topology also the pcb will from scratch. If you are anybody else has some answers here, they are most welcome....
Have a good meeting over there in SF. Anyway if ones you would have a meeting in Belgium let me know !
PS : schematic is here with the DC node voltage as tested and simulated. It also shows how it was AC simulated and reality measured the same way
Cheers
Olivier
For now there is no OPS in the circuit. The Vas output is the output node. My measurements for now are with the VAS unloaded by any resistor or anything else.
The transistors used are all 2SA1381 and 2SC3503 IPS & VAS.
However I would like to ask your specific opinion on one thing about pcb's. Imagine my PCB is 4 layered. Layer 1 Carries most op the power supply and higher voltage nodes, the rest of the layer is connected to a total copper pour in its turn connected to terminal (call it L1T). Layers 2 Is a 95% copper plane, it carries no tracks and it's only broken by the drill holes. The nearly full plane is connected to L2T. Layer 3 Conducts mainly track that are signal ground. This signal ground goes to a terminal Signal Ground. The rest of that layer, like in layer 1 is poured over with copper and led to a terminal L3T. Layer 4 carries other nodes and some tracks, just because layer 1 was cluttered and I didn't like it to run on the ground plane or signal ground plane. The rest of layer 4 is like layer 1 again, open spaces are poured up with copper and connected to a terminal L4T.
The idea was EMI reduction and mainly shielding.
Apart from guessing the best combination of tying L1T,L2T,L3T and L4T together and to what node like, common ground or decoupling ground or a combination again, it came up to me that these massive copper areas connected together and sandwishing tracks etc might provoke severe stray capacitance or parasitic capacitors?
Apart from the price is good to step up to multilayers to be able to have ground planes (if yes, full copper or hatched?) and is it wise to pour copper on the layers in order to fill the empty space with copper in turn connected to some ground. Maybe just pouring but not conected at all?
I will restart my circuit from scratch anyway using the same topology also the pcb will from scratch. If you are anybody else has some answers here, they are most welcome....
Have a good meeting over there in SF. Anyway if ones you would have a meeting in Belgium let me know !
PS : schematic is here with the DC node voltage as tested and simulated. It also shows how it was AC simulated and reality measured the same way
Cheers
Olivier
Hi Damir,
I understand your concern about stability of the Triple. To some extent, the more emitter followers, the more opportunities for parasitics that may cause oscillation. However, the Locanthi T circuit (3 EF Triple) is hard to beat for sound quality and low distortion. Amplifiers really do need that extra level of current gain between the output of the VAS and the load. This is especially true when working into low-impedance loads. You really want the load to be light on the VAS output node. It is also very important to recognize that beta droop and ft droop in the output transistors (and the drivers as well sometimes) really worsens the load under high-current conditions. I would flatly not make another amplifier with only a Double output stage.
Be careful with the layout of the Triple in regard to parasitics and the ability of high frequencies to sneak back to the early stages of the Triple on the rail. I usually put in some low-impedance R-C filtering in the rail line as it makes its way back from the output transistors to the drivers and to the pre-drivers. The filters also act as Zobel networks on the power rails, damping them at HF. This filtering need not drop hardly any rail voltage to be effective at the high frequencies where it is important. Drop between 0.1V and 1V at each stage of the filtering. Don't forget some base stoppers on the output transistors. I also like to put 10-50 ohms or so in the collector of the pre-driver.
Cheers,
Bob
Hello Bob,
I did simulate Triple output stage with same input as with dual emiter follower and I did get a bit better result, but no so better to go for practival build.
Here what I've got in the simulation:
1kHz 0.000003% (here a generator distortion was the same, so it looks as amp do not distort)
10kHz 0.000074%
20kHz 0.000299%
I attached LTSpice file with the schematic and models.
Could you tell if this amp, I have simulated, is wort to be built.
Thank you very much for your time.
Damir
I did simulate Triple output stage with same input as with dual emiter follower and I did get a bit better result, but no so better to go for practival build.
Here what I've got in the simulation:
1kHz 0.000003% (here a generator distortion was the same, so it looks as amp do not distort)
10kHz 0.000074%
20kHz 0.000299%
I attached LTSpice file with the schematic and models.
Could you tell if this amp, I have simulated, is wort to be built.
Thank you very much for your time.
Damir
Hi David,
I've also seen times when probing a circuit intrerferes with its operation or causes oscillation. Even when probing low-impedance nodes, like the output of an emitter follower, I will put a 100 ohm resistor in series with the probe at the test point to avoid oscillations that might be triggered by probe capacitance (much less of a problem if using a good 10 pF 10:1 probe). If I know that I will be probing several key points in a circuit, I'll sometimes solder free-standing 100 ohm resistors to them so that I can grab onto them with a probe at will. I note that other instruments, like meters, may pose a greater probing threat than a scope with a 10:1 probe.
When something goes wrong with a complex multi-loop circuit, like CMCL, it can be much more difficult to troubleshoot. In such a case, where possible, I may try to back off from the complex aspects of the circuit and simplify it enough to isolate problems.
Also, when working with circuits that are in an open-loop configuration at AC, funny things can happen at HF due to stray coupling because there is so much gain.
Cheers,
Bob
Thos are impressive level of THD. What was the peak output voltage? Does this apply to TMC or not?
Slew rate above 70V/us is great also.
By the way, I could run your first file while a file is missing for the last one.
Hello Bob ,
When you talk about beta droop and Ft droop( I assume output devices is what you are referring to) that with a triple EF output stage these effects have less of an effect on the VAS stage and consequently distortion is better, but surely the FT droop issue cannot be improved with a triple and still effects performance as much as it would with a double output stage.
When you say that you like to stick 10-50ohms or so in the collector of the pre-driver, you are referring to the first EF stage of the triple is this correct. Why don't you use stoppers in the base here, why is in the collector practically more effective.
Regards
Arthur .
Hi Andrew.
Not at all it's saves you from having to do a second PCB with updates or cut and solder to the bottom etc. If the pads are there one can use jumpers if B-Stoppers are not needed.
Same goes for compensation components.
I saw a lot of equipment out of Japan done this way.
David.
Hi Arthur,
Even ft droop effects are improved by the use of a triple as compared to a double, since total ac beta of the triple output stage is still much higher at high frequencies than with a double, resulting in less loading on the VAS at high frequencies where its output impedance is still a factor in spite of the shunt feedback provided by Miller compensation. Note that the pre-driver in a Triple usually has pretty good ft.
However, it is also still true that excess phase contributed in the output stage under ft droop conditions will not be improved by the use of a Triple as much as we'd like.
I have not compared the benefit of using base stoppers in the pre-driver as compared to a resistor in the pre-driver collector. I just use the collector resistor because it helps damp any HF resonance effects caused by collector inductance.
Note that I sometimes put a base stopper in the base of the driver transistor of a Triple.
Cheers,
Bob
it certainly appears in simulations that the forward gain/load isolation is much improved by the added VAS buffer/triple's extra Q - this should be a 100 MHz+ device and as such it adds almost no loop phase shift at the typical few MHz feedback loop gain intercept
the potential RF instabilities are expected to all be local PS mutual coupling and parasitic interaction problems - not easy to model or diagnose but problems should be solvable without audio loop gain compromise
the potential RF instabilities are expected to all be local PS mutual coupling and parasitic interaction problems - not easy to model or diagnose but problems should be solvable without audio loop gain compromise
Hi jcx,
These are all very good points. Local oscillations in output stages are tough to model, but are usually solvable by really good decoupling of the power supplies and appropriate use of techniques like base stoppers. The key is to prevent the formation of high-Q oscillator topologies.
Cheers,
Bob
Hi Olivier,
Board layout with more than two layers is nice, but it always means more different combinations to consider, and sometimes this is fairly subjective. I would first say not to worry too much about the capacitances to the ground/power planes.
Secondly, it is my style to put as much of the circuit wiring on the wiring side, then the reamainder of necessary signals on the component side. This makes that stuff accessible for toubleshooting and white wires. I would be inclined to put the ground plane directly beneath the wiring side, but I would be inclined to be free to use portions of it for a separate analog ground. Sometimes it is best to put islands in the plane, and those islands can be poured. I'd tend to put power on the plane beneath the component side, but again not hesistate to do a little bit of wiring on it. You may wish to put both pos and neg rails on this plane, and I don't think there is a need to pour it everywhere.
I would be cautious of running noisy power planes under signal circuits.
This is all very subjective, but it is nice to have four layers and have the "problem" of having to make these decisions.
I don't know how many others here are using four-layer boards, but it would be interested to hear their opinions.
Are you using ordinary FR4?
Cheers,
Bob
4 layer boards and other stuff
Hello Bob,
Thanks for you base/ collector stoppers response Bob.
JCX thanks for your insight , it takes a some experience to isolate these parasitic effects from the main feedback loop issues. What techniques do you use to isolate parasitic oscillation effects.
I have built amps with 4 layers and I tend to use top side (L1) for component wiring tracks, layers L2 and L3 are power supplies each layer is dedicated to one supply voltage, and layer L4 the bottom layer is the ground plane with a small number of component wiring tracks which would not fit on the top layer.
I find I split the ground plane into quite and noisy sections, all electrolytic capacitors ground returns are put onto the noisy section back to the star point.
I find so far I have not needed to route through the power planes. Also power planes are good all over (I think) because they eliminate inductance in the power supply wiring which can cause problems. Also close coupling of +/- supply rails (reducing loop area) is very important on the output stage where the heavy half wave currents are, in reducing even order distortion which is magnetically induced .
Regards
Arthur
Hello Bob,
Thanks for you base/ collector stoppers response Bob.
JCX thanks for your insight , it takes a some experience to isolate these parasitic effects from the main feedback loop issues. What techniques do you use to isolate parasitic oscillation effects.
I have built amps with 4 layers and I tend to use top side (L1) for component wiring tracks, layers L2 and L3 are power supplies each layer is dedicated to one supply voltage, and layer L4 the bottom layer is the ground plane with a small number of component wiring tracks which would not fit on the top layer.
I find I split the ground plane into quite and noisy sections, all electrolytic capacitors ground returns are put onto the noisy section back to the star point.
I find so far I have not needed to route through the power planes. Also power planes are good all over (I think) because they eliminate inductance in the power supply wiring which can cause problems. Also close coupling of +/- supply rails (reducing loop area) is very important on the output stage where the heavy half wave currents are, in reducing even order distortion which is magnetically induced .
Regards
Arthur
at audio frequencies plane currents are largely "resistance" controlled and do not "voluntarily" form mag field minimizing "image" currents under traces that make gnd/power planes so useful with high speed digital
driver and output devices really need dedicated, purpose designed power distribution to make the current/return loop paths as balanced "common centroid" as possible if you want to minimize radiated mag field from the more nonlinear currents - particularly with Class AB/B output
you also don’t want the nonlinear current returns completing by flowing across your clean front end gnd plane and giving common impedance coupling
way too many layouts posted here have +/- power entering from opposite edges of the boards - very wrong! - they should enter the board, be routed as close together as possible (with the possible exception of floating, independant secondary dual supplies where you can twist each power with its own return)
parasitic C from power planes may reduce PSRR at some points in the circuit - I definitely section/split, leave voids, and do "fat" power trace routing in my power layer in strain gage instrumentation boards - I have 8000x amplification, 16 bit ADC and 40 MHz DSP all running with in a few inches of each other on a single board
I have also seen too many simplistic "star gnd" layouts - I think about the current loops, and often have a "hierarchy" of gnd - with front end analog gnd often a plane but splits/slots define the branch to "dirty gnd" to keep large nonlinear (noisy digital mostly in my instrumentation) currents from "diffusing" into/across my clean analog gnd - and only flitered power should be routed over the clean gnd
driver and output devices really need dedicated, purpose designed power distribution to make the current/return loop paths as balanced "common centroid" as possible if you want to minimize radiated mag field from the more nonlinear currents - particularly with Class AB/B output
you also don’t want the nonlinear current returns completing by flowing across your clean front end gnd plane and giving common impedance coupling
way too many layouts posted here have +/- power entering from opposite edges of the boards - very wrong! - they should enter the board, be routed as close together as possible (with the possible exception of floating, independant secondary dual supplies where you can twist each power with its own return)
parasitic C from power planes may reduce PSRR at some points in the circuit - I definitely section/split, leave voids, and do "fat" power trace routing in my power layer in strain gage instrumentation boards - I have 8000x amplification, 16 bit ADC and 40 MHz DSP all running with in a few inches of each other on a single board
I have also seen too many simplistic "star gnd" layouts - I think about the current loops, and often have a "hierarchy" of gnd - with front end analog gnd often a plane but splits/slots define the branch to "dirty gnd" to keep large nonlinear (noisy digital mostly in my instrumentation) currents from "diffusing" into/across my clean analog gnd - and only flitered power should be routed over the clean gnd
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4 Layer
Hello jcx
>driver and output devices really need dedicated, purpose designed power distribution to make the current/return loop paths as balanced "common centroid" as possible if you want to minimize radiated mag field from the more nonlinear currents - particularly with Class AB/B output
I use 4Layer boards specifically for the output stage Class AB/B output nonlinear current problem. My experience has been that the loop area of the +/- must be as small as possible, starting with power supply entry into the PCB board the +/- supply wiring is very close together, these tracks that carry these currents through the pcb should also be very close together and with +/- power planes this is a very good way to achieve this.
The input ground should be separate to the noisy ground these grounds are connected together with 10 ohms but have there own separate connection to the star point.
Regards
Arthur
Hello jcx
>driver and output devices really need dedicated, purpose designed power distribution to make the current/return loop paths as balanced "common centroid" as possible if you want to minimize radiated mag field from the more nonlinear currents - particularly with Class AB/B output
I use 4Layer boards specifically for the output stage Class AB/B output nonlinear current problem. My experience has been that the loop area of the +/- must be as small as possible, starting with power supply entry into the PCB board the +/- supply wiring is very close together, these tracks that carry these currents through the pcb should also be very close together and with +/- power planes this is a very good way to achieve this.
The input ground should be separate to the noisy ground these grounds are connected together with 10 ohms but have there own separate connection to the star point.
Regards
Arthur