@stellarelephant: Wow! - very impressive condensation of Bateman's capacitor articles ;-)
One comment on this ... Some time ago I saw some dissipation factor vs. frequency curves for Panasonic SMD PPS capacitors. While low (and comparable to C0G) in the lower frequencies they showed an almost vertical rise in DF just above 1 MHz. In comparison C0G capacitors to my knowledge show almost no difference when going up in frequency.
In general - when considering SMD capacitors (digital HF decoupling
) - size does indeed matter and what to do except for using high distortion capacitors like e.g. X7R ??? I am quite sure that these capacitors' sound in most cases reflect into the sound circuitries, however, using e.g. a 10 uF polypropylene to decouple a DAC is not very effective (at all) with a lead spacing of maybe 20 mms ... So ... Anyone have found some good sounding SMD capacitors?
Cheers,
Jesper
One comment on this ... Some time ago I saw some dissipation factor vs. frequency curves for Panasonic SMD PPS capacitors. While low (and comparable to C0G) in the lower frequencies they showed an almost vertical rise in DF just above 1 MHz. In comparison C0G capacitors to my knowledge show almost no difference when going up in frequency.
In general - when considering SMD capacitors (digital HF decoupling
) - size does indeed matter and what to do except for using high distortion capacitors like e.g. X7R ??? I am quite sure that these capacitors' sound in most cases reflect into the sound circuitries, however, using e.g. a 10 uF polypropylene to decouple a DAC is not very effective (at all) with a lead spacing of maybe 20 mms ... So ... Anyone have found some good sounding SMD capacitors?Cheers,
Jesper
Sorry, but it is not still clear enough what this bias means and how it's applied.
In some cap applications, such as an interstage cap used in a transistor amplifier, a DC voltage will appear across the cap naturally, and that DC voltage placed across the cap by the circuit would be the DC bias voltage. In a test setup, you can use a DC source, connect it to a resistor, and then to the cap in order to charge the cap up to that DC voltage. Then, when you test, the AC test signal will be added to the DC already on the cap, and the resulting total voltage is what's applied to the cap.
However, read my post. The notion that there's an "ideal DC bias" is I think a faulty observation caused by the nature of distortion testing. I claim that it doesn't exist - capacitor distortion is purely an increasing function of drive level, and there is no magic null. The null is observed in the distortion vs. level data only because the distortion analyzer has residual distortion of its own, which destructively sums with the distortion of the cap being tested, creating a "null" when the distortion of the cap and the distortion of the analyzer have the same magnitude but opposite polarity. This happens easily with 2nd harmonic, and I have observed it often, not just in capacitors, but also in ferrite beads and complete amplifiers. It's an analyzer phenomenon, not a capacitor phenomenon.
@carlmart:
I have actually drawn up a circuitry for you in #1016 that shows how the bias is applied...
Jesper
You have to put a resistor between the DC bias source and the cap under test, or else the DC bias source, being a voltage source with low impedance, will short out the AC voltage across the cap. Of course, not perfectly, but if you don't, you're measuring a voltage divider between the AC source impedance and the DC bias source impedance - not what you intended.
That resistor has to be scaled with the size of the DUT cap in mind. It has to charge up the DUT, so it can't be very big at all. In my test jig, a 2K2Ω resistor take a while to charge up 470µF, but I can wait a minute or so. Burn in time, right
Very interesting, McGuire. But this concept of optimum bias have been applied in many places such as at the input of an amplifier and in crossover networks. With this fact, it is hard to believe that no-one has actually heard the difference!!!??
Nothing. This is about sinusoidal signal (AC) distortion. So mainly a coupling capacitor for audio signal. The voltage is often almost zero and some people have tried to bias the cap to achieve this optimum distortion.
In power supply we mostly deal with DC. The AC part is the NOISE that we try to shunt to ground using RC and low ESR capacitor.
Monte, your theory about the analyzer nulling cap distortion is good food for thought. I know Bateman built a pretty elaborate purpose-made test rig (he shared the schematic in the series), so I always assumed he'd avoided such pitfalls.
Flawed or not, probably the best chance to use the "optimal bias" concept (or the H2/H3 "sweet spot" concept I prefer) is in the output of an AC coupled amplifier, where the low load impedance demands a high capacitance not achievable with film caps. I certainly prefer to use films wherever possible. BUT then again, Nelson Pass and others often favor Silmic II for coupling even in such cases.
Flawed or not, probably the best chance to use the "optimal bias" concept (or the H2/H3 "sweet spot" concept I prefer) is in the output of an AC coupled amplifier, where the low load impedance demands a high capacitance not achievable with film caps. I certainly prefer to use films wherever possible. BUT then again, Nelson Pass and others often favor Silmic II for coupling even in such cases.
@Monte McGuire:
Of course - I also have it on the PCB I use to bias the capacitors but apparently forgot in on the PCB Thanks for "seeing" this!
And to carlmart if you read this: There should be a resistor of some value, e.g. 2k2 or lower value, between the Bias_in input and the C2/C3 common node in the schematic in post #1016.
Cheers,
Jesper
Of course - I also have it on the PCB I use to bias the capacitors but apparently forgot in on the PCB
Thanks for "seeing" this!And to carlmart if you read this: There should be a resistor of some value, e.g. 2k2 or lower value, between the Bias_in input and the C2/C3 common node in the schematic in post #1016.
Cheers,
Jesper
Should have been: Of course - I also have it on the PCB I use to condition the capacitors but apparently forgot in on the schematic (in #1016) ..
... Jesper ...
I suspected so, but just wanted to point that out in case someone builds it without thinking enough and gets odd results. Life is so complicated, right??
... comes to my mind ... Hi sumotan (don't know if this is your name - I am not familiar with Indonesian names ;-))..
Basically "bias" is the voltage applied across the capacitor. Thus, e.g. when a capacitor is used in a +/- 15 VDC power supply the "bias" across the capacitor here would be 15 volts (for each of the negative & positive supply voltages). When used as a coupling capacitor the bias across the capacitor would be the voltage difference between the two circuit "nodes" that this coupling capacitor connects between. Hope this is reasonably clear ... ?
The thing is that capacitor distortion rises significantly when the bias voltage goes up from just very low voltages. As stellarelephant points out in #1200 (and also noted in cyril bateman's 6th article on capacitor distortion) 2H distortion is lowest at very low bias voltages (e.g. at 4 volts for a 50 VDC rated capacitor). Monte McGuire also has some thoughts about this in the top post on this page #1211.
Hope this helps.
Cheers,
Jesper
Basically "bias" is the voltage applied across the capacitor. Thus, e.g. when a capacitor is used in a +/- 15 VDC power supply the "bias" across the capacitor here would be 15 volts (for each of the negative & positive supply voltages). When used as a coupling capacitor the bias across the capacitor would be the voltage difference between the two circuit "nodes" that this coupling capacitor connects between. Hope this is reasonably clear ... ?
The thing is that capacitor distortion rises significantly when the bias voltage goes up from just very low voltages. As stellarelephant points out in #1200 (and also noted in cyril bateman's 6th article on capacitor distortion) 2H distortion is lowest at very low bias voltages (e.g. at 4 volts for a 50 VDC rated capacitor). Monte McGuire also has some thoughts about this in the top post on this page #1211.
Hope this helps.
Cheers,
Jesper
Pardon me for jumping in here, but many times, regulators require an output capacitor in order to be stable, so you don't have that luxury. The circuits I'm working on now use the Analog Devices ADP7142 and ADP7182 regulators, and they require 1.5µF of capacitance at their output in order to operate properly. Yes, this is a small value, and these capacitors can be ceramics or other low impedance caps, but it forces me to place bypass caps in the circuit to keep these regulators happy. The only good part is that amplifier ICs also like to have small bypass caps near them in order to assure a wideband, low impedance power supply, so the required bypass capacitance can be split into a few smaller caps placed near each chip, solving both problems at once.
May be it will be clearer if we stated that we are talking about DC bias across a capacitor that will pass AC signal (i.e. audio signal, or a sinusoidal test signal to represent the audio/music).
An extreme example is in speaker crossover where there is only AC (DC will blows the driver). There is no potential difference (DC) between the leads of a capacitor. Some speaker manufacturers bias the caps with batteries.
In amplifiers with single rail supply, the output cap is automatically DC biased because there is DC (half the rail) at the output.
We can avoid capacitors at AC signal path of an amplifier's input (DC coupled) and uses several techniques to avoid DC appears at the output (such as using DC servo), but in DC power supply we can't avoid the capacitor, can we?