Thanks for the tip. Would you know the value of this fuse? I never knew SMD fuses existed! What would be a way to find out if the in place fuse is blown or not?
While the fuse is in place on the PCB, using a DMM on the continuity setting, gives a beep across the two legs of the fuse. I believe it is alright. Where to look next?
Hello, @smooth dancer ! Just curious, did you test Accusilicon clocks on Q7? There is a post of @khh who said "tried my Accusilicon AS318 clocks but they will not play music, red led showing empty. This Accusilicon clocks was used all the time on Q2 until i swapped to Q7."
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hello, sorry for my Englisch ,
I,am reading and looking for info and help .
But i Can not find good info ore i don,t geht it
What i want to bild is this Rasperry pi direct to NOS TDA1541a S1 Dac .
This is the 44,1/48 Family so a old r2r dac.
Does Ian Canada have a selution for this ?
???? IAN CANADA FIFOPIMA V 1.5 ??????
Thanks for help ore info.
Bart Wolters.
I,am reading and looking for info and help .
But i Can not find good info ore i don,t geht it
What i want to bild is this Rasperry pi direct to NOS TDA1541a S1 Dac .
This is the 44,1/48 Family so a old r2r dac.
Does Ian Canada have a selution for this ?
???? IAN CANADA FIFOPIMA V 1.5 ??????
Thanks for help ore info.
Bart Wolters.
Hello @iancanada ,
Please can you give details about StationPiPro J6 logic and aplication? I saw on the StationPiProSchV1.0: ON/OFF, ROTARY0, ROTARY1, IR.
Thank you!
I recently tested several clocks on my Q7. This was to weed out some I had thought were bad. Accusilicon was among them. I found they work just fine. Just keep in mind the frequency of the clock 'family' needs to support the incoming signal. I had been using the 'stock' clocks (45.1584 & 49.1520), now I'm going to move up to higher clock freq. (90.3168 & 98.3040) to support the higher res files I have. I'm using Crystek clocks in my main system now, and completely happy with the sound.
Hi redjr,
Please no worries, I have Accusilicon clocks, here is the solution:
A few kinds of XO clocks, such as an Accusilicon, have very strong internal pull-up resistors on the OE pin which could result in a wrong logic level to the XO selection signal of FifoPiQ7. However, FifoPiQ7 doesn't need that OE pin. If that's the case, please just bend or simply remove the pin1 of those XOs so that the pin1 doesn’t be plugged in the XO socket.
The other solution is that you can just connect a 1k resistor between pin1 (OE) and pin4 (GND) of the clock.
For more details, please read the Q7 user's manual troubleshooting section
https://github.com/iancanada/DocumentDownload/blob/master/FifoPi/FifoPiQ7/FifoPiQ7Manual.pdf
The issue will be solved.
Good luck to your project
Happy Halloween!
Ian
hello, I would just like someone to explain to me how to wire the isolatorpi and the fifopima in masterclock mode.
Sorry but I do not fully master English and even when translating I admit that I am a bit lost.
For me, you have to superimpose the isolator on the raspi and fifopima on the isolator then wire the isolator and fifopima by ufl master cable and set j12 and j13 in master mode on the isolator.
On the other hand, from fifopima to the dac, I could use the second ufl j11 output to stay in masterclock mode?
Sorry but I do not fully master English and even when translating I admit that I am a bit lost.
For me, you have to superimpose the isolator on the raspi and fifopima on the isolator then wire the isolator and fifopima by ufl master cable and set j12 and j13 in master mode on the isolator.
On the other hand, from fifopima to the dac, I could use the second ufl j11 output to stay in masterclock mode?
Sorry for the confusion Ian. My phrasing could have been better re "Accusilicon was among them" I didn't mean to imply the Accusilicon clocks were bad. The ones I have are working fine for the frequencies they support - even with pin 1 inserted. I have not tried any with pin 1 cut off. I did note in your Q7 docs (page 17 #5) about loose connections. I need to get some of those 4-pin SMD sockets, because mine are very loose and should be replaced.Hi redjr,
Please no worries, I have Accusilicon clocks, here is the solution:
A few kinds of XO clocks, such as an Accusilicon, have very strong internal pull-up resistors on the OE pin which could result in a wrong logic level to the XO selection signal of FifoPiQ7. However, FifoPiQ7 doesn't need that OE pin. If that's the case, please just bend or simply remove the pin1 of those XOs so that the pin1 doesn’t be plugged in the XO socket.
The other solution is that you can just connect a 1k resistor between pin1 (OE) and pin4 (GND) of the clock.
For more details, please read the Q7 user's manual troubleshooting section
https://github.com/iancanada/DocumentDownload/blob/master/FifoPi/FifoPiQ7/FifoPiQ7Manual.pdf
The issue will be solved.
Good luck to your project
Happy Halloween!
Ian
Please find #45A SMT XO socket, it could be what you are looking for.
https://github.com/iancanada/DocumentDownload
Ian
@Ian,
Sorry I missed this before posting.
Where do you source the 4-pin (with right angle mounting pins) sockets used for the clocks at U13 and U7. Part number? I can't find them anywhere on the web, or even images of them. Maybe I'm not describing them correctly in my searches.
Sorry I missed this before posting.
Where do you source the 4-pin (with right angle mounting pins) sockets used for the clocks at U13 and U7. Part number? I can't find them anywhere on the web, or even images of them. Maybe I'm not describing them correctly in my searches.
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Please read the FifoPiMa V1.5 User's manual IsolatorPi section
https://github.com/iancanada/DocumentDownload/blob/master/FifoPi/FifoPiMa/FifoPiMaManualV1.5.pdf
Please let me know if you have more questions.
Ian
OK, I just re-read the manuals again.
I think I hadn't understood that the master clock mode should only come, in my case, from fifopima, so the J6 or J11 output to a dac or digital hat but whether it's from the isolator to the fifo, i2s can either by gpio or ufl SCK LRCK SD is that the correct answer this time?
I think I hadn't understood that the master clock mode should only come, in my case, from fifopima, so the J6 or J11 output to a dac or digital hat but whether it's from the isolator to the fifo, i2s can either by gpio or ufl SCK LRCK SD is that the correct answer this time?
1. All I2S signals have to be connected from FifoPiMa to your DAC
2. SCK, LRCK and SD can be taken either from GPIO or from u.fl connectors. u.fl coaxial cables have better signal quality so they are recommended. But taking from GPIO can be easier so is still OK.
3. If you DAC needs MCLK, you can take either from J6 or from J17 on FifoPiMa, they are equivalent.