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Joined 2006
Joachim's buffer could also be used for NOS dacs to "help clean up the HF dirt", could it?
Read with interest the comparison of PCM1704 and PCM1794 (filter disable) - with and without external filtering (FPGA filter or filtering in software) by John Swenson.
(Google: Tony's Player, John Swenson)
BTW, thanks very much to you guys that have involved on the design and the GB of the buffer : )
Read with interest the comparison of PCM1704 and PCM1794 (filter disable) - with and without external filtering (FPGA filter or filtering in software) by John Swenson.
(Google: Tony's Player, John Swenson)
BTW, thanks very much to you guys that have involved on the design and the GB of the buffer : )
Hi WK,
Attach are the close-up on the buffer, the 0603 package is just a bit too small for my eye. Although only a few passive components but I couldn't find the fault on the right channel.
Left channel (working)
Voltage measure across
R7 and R8 is 0.143V
R1 is 0
R2 is 0
Right channel (not working)
Voltage measure across
R7 and R8 is 0.496 (-Vs) and 0.491 (+Vs)
R1 is 5.226
R2 is 2.36
Thanks for your help.
Attach are the close-up on the buffer, the 0603 package is just a bit too small for my eye. Although only a few passive components but I couldn't find the fault on the right channel.
Left channel (working)
Voltage measure across
R7 and R8 is 0.143V
R1 is 0
R2 is 0
Right channel (not working)
Voltage measure across
R7 and R8 is 0.496 (-Vs) and 0.491 (+Vs)
R1 is 5.226
R2 is 2.36
Thanks for your help.
The 100R resistor of the right channel next to the silk screened letters "Gnd" is shorted to the JFET cascode source pin (first photo top right).
Suck out the solder with a solder wick to see if it will work.
If not I am afraid you might need to have the FETs replaced.
We'll mask off those pads in Batch 2 to avoid such "accidents".
But it also helps when you check the boards thoroughly for such soldering errors before power up.
It is also a great help to use a ring lamp with a magnifying glass in the middle for AMD work.
Works fine even down to 0402s for my 50+ years old eyes, with short sightedness on top.
Patrick
Suck out the solder with a solder wick to see if it will work.
If not I am afraid you might need to have the FETs replaced.
We'll mask off those pads in Batch 2 to avoid such "accidents".
But it also helps when you check the boards thoroughly for such soldering errors before power up.
It is also a great help to use a ring lamp with a magnifying glass in the middle for AMD work.
Works fine even down to 0402s for my 50+ years old eyes, with short sightedness on top.
Patrick
Also judging from the photos, you seem to be using a ceramic cap instead of the Panasonic PPS film cap we recommended :
http://www.diyaudio.com/forums/grou...rhard-filter-buffer-es9022-3.html#post3113690
IMHO this will make a significant difference in results.
Suggest you try the Panasonic caps to convince yourself.
Patrick
http://www.diyaudio.com/forums/grou...rhard-filter-buffer-es9022-3.html#post3113690
IMHO this will make a significant difference in results.
Suggest you try the Panasonic caps to convince yourself.
Patrick
Couldn't get the 0603 Panasonic PPS film cap from Element14 so I use the MLCC instead, will try PPS when I batch enough to meet Mouser's/Digikey minimum order.
Thanks
@ EUVL (and all)
I am about to setup my own ES9023 system with WM8805 and JG Filter Buffer (could have joined the several GB but wanted to DIY
).
In post #58 you mentioned using two flip flops to devide the masterclock 1:4 for SD player (or WM8805?). What about the propagation delay of the flip flops? As per the datasheets the delay is about 2-10ns per flip-flop which sums up to a 4-20ns delay for the 1:4 devider. This is in the order of a period of the masterclock. Will the system still work in synchronous mode or will it work in asynchronous mode due to the delay (MCLK phase shift)?
Furthermore random phase jitter of good clock oszilators is specified as arround 1ps. For the propagation delay of the flip-flops the datasheet only specify min. and max. values (component variation?). Do you have any information about the variation of the propagation delay for a single flip-flop (that would add jitter)?
Best regards, Daniel
I am about to setup my own ES9023 system with WM8805 and JG Filter Buffer (could have joined the several GB but wanted to DIY
). In post #58 you mentioned using two flip flops to devide the masterclock 1:4 for SD player (or WM8805?). What about the propagation delay of the flip flops? As per the datasheets the delay is about 2-10ns per flip-flop which sums up to a 4-20ns delay for the 1:4 devider. This is in the order of a period of the masterclock. Will the system still work in synchronous mode or will it work in asynchronous mode due to the delay (MCLK phase shift)?
Furthermore random phase jitter of good clock oszilators is specified as arround 1ps. For the propagation delay of the flip-flops the datasheet only specify min. and max. values (component variation?). Do you have any information about the variation of the propagation delay for a single flip-flop (that would add jitter)?
Best regards, Daniel
Firstly for Red book CD, LRCK = 44.1kHz, BCK = 2.8224MHz, SCK =45.1584MHz in my case.
So there are 16 system clock pulses within one bit clock.
There is next to no information in the ES9023 datasheet regarding timing requirement between SD, BCK & LRCK to SCK.
However, on P.12 of the PCM5102 datasheet, “The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.” I have no reason not to believe that it does not hold for ES9022 and the like.
On my original QA550 PCB, for example, the 11.28MHz XO feeds both the dsPIC and the SCK output directly. The dsPIC itself have multiple internal delays in double digit ns if I am not wrong. In comparison, the D-FF I use in my frequency divider has a propagation delay of under 1ns. Information from the manufacturer’s technical service indicates that the additional jitter per FF is < 1ps.
I don't claim to be a DAC expert by any means, but my understanding is that as long as SD, BCK and LRCK is synchronised relative to each other, and that they have the same base frequency of the SCK, which exact pulse of the SCK it is locked onto by the DAC does not matter. The synchronisation of SD, BCK and LRCK is implemented by your digital source (good or bad), and the fact that the same XO drives both the DAC and the digital source means that they are always in syn (phase relationship constant).
The SPDIF input of the WM8804(5) is of course a totally different matter. I am sure you know there is a PLL inside the WM8804, as it is necessary.
Hope this helps.
Patrick
So there are 16 system clock pulses within one bit clock.
There is next to no information in the ES9023 datasheet regarding timing requirement between SD, BCK & LRCK to SCK.
However, on P.12 of the PCM5102 datasheet, “The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock.” I have no reason not to believe that it does not hold for ES9022 and the like.
On my original QA550 PCB, for example, the 11.28MHz XO feeds both the dsPIC and the SCK output directly. The dsPIC itself have multiple internal delays in double digit ns if I am not wrong. In comparison, the D-FF I use in my frequency divider has a propagation delay of under 1ns. Information from the manufacturer’s technical service indicates that the additional jitter per FF is < 1ps.
I don't claim to be a DAC expert by any means, but my understanding is that as long as SD, BCK and LRCK is synchronised relative to each other, and that they have the same base frequency of the SCK, which exact pulse of the SCK it is locked onto by the DAC does not matter. The synchronisation of SD, BCK and LRCK is implemented by your digital source (good or bad), and the fact that the same XO drives both the DAC and the digital source means that they are always in syn (phase relationship constant).
The SPDIF input of the WM8804(5) is of course a totally different matter. I am sure you know there is a PLL inside the WM8804, as it is necessary.
Hope this helps.
Patrick
Thanks EUVL, that definately helps!
As you said, ES9023 datasheet does not say anything about timing requirement (thats why I asked) but I didn't look to other datasheets...
May I ask which D-FF you use. A short search at Mouser only showed me parts with 2.4 and higher propagation delays (wouldn't be a problem though if exact phase relation isn't required) and the datasheets (only looked into few) don't specify added jitter (propagation delay variation).
Daniel
As you said, ES9023 datasheet does not say anything about timing requirement (thats why I asked) but I didn't look to other datasheets...
May I ask which D-FF you use. A short search at Mouser only showed me parts with 2.4 and higher propagation delays (wouldn't be a problem though if exact phase relation isn't required) and the datasheets (only looked into few) don't specify added jitter (propagation delay variation).
Daniel
Hi Patrick,
The solder was cleaned up, reconfirmed that there is no other mistake, I powerup with 2 9V battery and it is working, the Jfet seems ok. After playing for few hours and ran out of battery so I will need to build a 12V +/- regulated power supply for it. One quick observation is the music play back has more body. I will know more after finishing the PS.
Thanks for your help.
Hi WK,
Thanks for the PPS cap, I replaced the MLCC with them and I can tell you that the difference is quite significant! The 9V battery only last for 2+ hrs and I built a +/-12V supper reg for it. I have been listening to it for over 4 hours yesterday, the sound is more sweet and didnot notice any harshness, slight forward presentation. Key thing is the JG filter transformed the 9023 dac to another level. All the listening was done on the dac with a 3875 chipamp, need to build a balance version for my Rowland.
Note: I didn't remove the 4700pf cap on the 9023 output, will try that this week. I also use 10K for R1 according to Patrick's latest JG filter Public 121217.pdf instead of the Joachim's 18.9K, will that make a large difference?
Thanks
Thanks for the PPS cap, I replaced the MLCC with them and I can tell you that the difference is quite significant! The 9V battery only last for 2+ hrs and I built a +/-12V supper reg for it. I have been listening to it for over 4 hours yesterday, the sound is more sweet and didnot notice any harshness, slight forward presentation. Key thing is the JG filter transformed the 9023 dac to another level. All the listening was done on the dac with a 3875 chipamp, need to build a balance version for my Rowland.
Note: I didn't remove the 4700pf cap on the 9023 output, will try that this week. I also use 10K for R1 according to Patrick's latest JG filter Public 121217.pdf instead of the Joachim's 18.9K, will that make a large difference?
Thanks
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Joachim included the 4700pF cap in his filter calculations, thus removing this would change one pole of the filter. Therefore it should not be removed.
Not sure though about the exact value of R1 of the latest version. The latest BOM
does not include the 18.7kOhm resistor, however according to the Fastron Inductor Group Buy thread, XEN audio provided similar values (18.9kOhm) to FRAN for the Kits.
Maybe it is possible for EUVL or Fran or JG to post the latest BOM just to avoid any misunderstandings?
Best regards, Daniel
Not sure though about the exact value of R1 of the latest version. The latest BOM
does not include the 18.7kOhm resistor, however according to the Fastron Inductor Group Buy thread, XEN audio provided similar values (18.9kOhm) to FRAN for the Kits.
Maybe it is possible for EUVL or Fran or JG to post the latest BOM just to avoid any misunderstandings?
Best regards, Daniel
> I didn't remove the 4700pf cap on the 9023 output, will try that this week.
You should not.
It is designed to work with the 4.7nF in place.
If you use other DAC from other people (e.g. a PCM5102) then you need to add an RC of 240R 4.7n at the output, before the JG filter.
I never intended to post the BoM in the forum, as I cannot do revision here.
I shall definitely not do it again.
So in the future subscribers will get either paper copies, or download from our website.
Also it is a matter of taste. We use 10k ourselves.
But Joachim prefers 18.7k.
Patrick
You should not.
It is designed to work with the 4.7nF in place.
If you use other DAC from other people (e.g. a PCM5102) then you need to add an RC of 240R 4.7n at the output, before the JG filter.
I never intended to post the BoM in the forum, as I cannot do revision here.
I shall definitely not do it again.
So in the future subscribers will get either paper copies, or download from our website.
Also it is a matter of taste. We use 10k ourselves.
But Joachim prefers 18.7k.
Patrick
If I pose another version here, I invite more questions about which version is most update, at what post, preferably with links .....,
which cost me time that I do not have.
So for the simple sake of version management, we need to do things differently.
Things you don't think about till you have to run these things over x batches.
Easy for you to ask.
Every such request requires hours of work ....
Patrick
which cost me time that I do not have.
So for the simple sake of version management, we need to do things differently.
Things you don't think about till you have to run these things over x batches.
Easy for you to ask.
Every such request requires hours of work ....
Patrick
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