I forgot to mention, if you are using the isolator, the optional 3rd isolator chip is a 2 way device designed for isolating the i2c for example from the MCU. you can use it for anything you like of course, but it would be counterproductive to isolate everything then circumvent it with the MCU USB connection
youre right its only indicated with the 192khz light by itself, think thats an error, since you mentioned it I remember briefly testing 384 with amanero and not getting the right indication for 384. i've only had fifo with v3.3 FW back for a few weeks and its been ******* down for a lot of it, too humid for operating a dac like this with the top off, I had a disconcerting slight hissing sound (no smoke but enough to make me switch off immediately) when I turned it on last week... I know after that crazy horizontal rain we had, some of the light fittings were dripping while I was asleep, so I packed it away in a box all this week with some crystals and baking soda. theres nothing directly above where the dac was, but one not far away, could have got a touch of spray, nothing else could have been wrong as it had been fully operational the day before.
The MCU (AKC12) USB serial comms is low speed LVTTL and can also be isolated similarly, e.g. using an IL716 chip for the TX/RX lines
yeah thats what I was suggesting, the siliconlabs chips are not a bad option either, like Si8440BB/Si8441BB/Si8442BB. so the i2c, or the 'USB' can be isolated, either or wouldnt seem to make a lot of difference. I would think doing the i2c would again be preferred because its the last minute so any possible noise on ground from the MCU is avoided. not suggesting that is an issue, but why not if you can?
Master Clock for AKD16
Master clock can be from the transport MCLK output. This is usually available and will be very straightforward to connect directly, 3.3V logic (Synchronous mode and no extra cost). Alternatively, dedicated clock modules (e.g. Crystek CCHD series) can be used up to 100MHz for the 9016 DAC. More elaborate ones like the AKX701 provide even further options.
Master clock can be from the transport MCLK output. This is usually available and will be very straightforward to connect directly, 3.3V logic (Synchronous mode and no extra cost). Alternatively, dedicated clock modules (e.g. Crystek CCHD series) can be used up to 100MHz for the 9016 DAC. More elaborate ones like the AKX701 provide even further options.
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Turbo Re-Clocker AKL series ...
Folks,
This is another attempt to get the EX2UI board to work with the Turbo Clock (AKX701) unit. (In my previous post I highlighted some difficulties)
The EXA unit has a FIFO-buffer + dual clock on a compact board, all great for jitter elimination. However, the I2S output signals go through isolator chips (IL715) and thereby gets slightly degraded (jitter-wise). The reclocker module (AKL series) serves to clean up the I2s signals from the EXA unit. The reclocked + bufffered outputs are on w.fl coax headers to match the DAC module (AKD12P). Pin headers from the AKL connect directly to the EXA2UI output terminal block as shown.
The re-clock Flip-flops are clocked by the same MCLK as that of the DAC (100M). Used this way results in Async Re-Clocking.
I have also added Clock isolator on board so that the divided slave clocks from the AKX701 Clock module can be safely piped into the EX2UI for Sychronous Re-Clocking. As the reclock MCLK freq is much higher (100M) than the transport clocks (25M), I am hoping that this 'Turbo' reclocking technique will be able handle higher sample rates without problems.
Also added on board is a Sample Rate DAQ and transmitter (I2C comms). The MCU can read Fs direct from the transport and display accordingly.
Shown is 2CH version. 8CH with AKD18 DAC, similarly.
Other tranports can similarly benefit from this arrangment and I will be rolling these out soon.
Folks,
This is another attempt to get the EX2UI board to work with the Turbo Clock (AKX701) unit. (In my previous post I highlighted some difficulties)
The EXA unit has a FIFO-buffer + dual clock on a compact board, all great for jitter elimination. However, the I2S output signals go through isolator chips (IL715) and thereby gets slightly degraded (jitter-wise). The reclocker module (AKL series) serves to clean up the I2s signals from the EXA unit. The reclocked + bufffered outputs are on w.fl coax headers to match the DAC module (AKD12P). Pin headers from the AKL connect directly to the EXA2UI output terminal block as shown.
The re-clock Flip-flops are clocked by the same MCLK as that of the DAC (100M). Used this way results in Async Re-Clocking.
I have also added Clock isolator on board so that the divided slave clocks from the AKX701 Clock module can be safely piped into the EX2UI for Sychronous Re-Clocking. As the reclock MCLK freq is much higher (100M) than the transport clocks (25M), I am hoping that this 'Turbo' reclocking technique will be able handle higher sample rates without problems.
Also added on board is a Sample Rate DAQ and transmitter (I2C comms). The MCU can read Fs direct from the transport and display accordingly.
Shown is 2CH version. 8CH with AKD18 DAC, similarly.
Other tranports can similarly benefit from this arrangment and I will be rolling these out soon.
Attachments
AKL Series
Yes, it will be. Finalising design... Still tossing between the easy to get TI FFs (3ns) or the PotSemi ones (<2ns)
Yes, it will be. Finalising design... Still tossing between the easy to get TI FFs (3ns) or the PotSemi ones (<2ns)
Asynchronous re-clocking...
There was a discussion precisely on this method of reclocking over at my blog a few days ago. I concluded that because the clock speed is much higher than the sample rate, the reclocking is always bit-perfect.
However, the width of the pulses (eg bitclock) will be changing, modulated by the 100MHz clock. What are your thoughts on this?
There was a discussion precisely on this method of reclocking over at my blog a few days ago. I concluded that because the clock speed is much higher than the sample rate, the reclocking is always bit-perfect.
However, the width of the pulses (eg bitclock) will be changing, modulated by the 100MHz clock. What are your thoughts on this?
Async Re-Clocking
Thanks GLT, very interesting convergence of ideas from different parties
You have also nailed it nicely in your blog that I only vaguely managed to imagine! Again the scope of my plan is Sync Re-Clocking really with the AKX701 that is easy to frame and analyse the timing. It then became obvious if a simple DAC MLCK is used and no transport interaction then it defaults to ASync Re-Clocking. ASync re-clocking has been used since the beginning of times e.g. Typical Application
I haven't analysed the detailed timing but would assume at 100MHz reclock on say, 500KHz Fs bitclock would not cause problems even if not synchronised. Also, if it has worked for the above implementation then we are assured?
BTW, all lines BCK, LRCK and SDA are re-clocked for my version.
Any further thoughts most welcome
Thanks GLT, very interesting convergence of ideas from different parties
You have also nailed it nicely in your blog that I only vaguely managed to imagine! Again the scope of my plan is Sync Re-Clocking really with the AKX701 that is easy to frame and analyse the timing. It then became obvious if a simple DAC MLCK is used and no transport interaction then it defaults to ASync Re-Clocking. ASync re-clocking has been used since the beginning of times e.g. Typical Application
I haven't analysed the detailed timing but would assume at 100MHz reclock on say, 500KHz Fs bitclock would not cause problems even if not synchronised. Also, if it has worked for the above implementation then we are assured?
BTW, all lines BCK, LRCK and SDA are re-clocked for my version.
Any further thoughts most welcome
Thanks GLT, very interesting convergence of ideas from different parties
...ASync re-clocking has been used since the beginning of times e.g. Typical Application
...
BTW, all lines BCK, LRCK and SDA are re-clocked for my version.
Any further thoughts most welcome
You are right! This stuff is ancient. Thanks for the link...
exa065 said on his post in exaDevices thread,
http://www.diyaudio.com/forums/exadevices/183374-exau2i-multi-channel-asynchronous-usb-i2s-interface-125.html#post3237290
How do you feel about his notice?
Thanks for the feedback
Yes, the EXA sound great of its own with this DAC but we need to test this case or see if further improvements can be made (Async mode). This idea is to reduce or eliminate jitter altogether before reaching the DAC so that the DAC does the final clean up to make it sound even better.
It will be fairly easy to do A/B comparison with my own DAC. There is no re-clocker circuit on the DAC board itself so we can insert an external re-clocker board (like the AKL module) between the DAC and the EXA unit. No mods
Dear acko,
I am much satisfied with your profound answer!
If you want a better result on USB, I'd like to recommend the use of this optical isolator.
http://www.diyaudio.com/forums/exadevices/183374-exau2i-multi-channel-asynchronous-usb-i2s-interface-125.html#post3236910
I am much satisfied with your profound answer!
If you want a better result on USB, I'd like to recommend the use of this optical isolator.
http://www.diyaudio.com/forums/exadevices/183374-exau2i-multi-channel-asynchronous-usb-i2s-interface-125.html#post3236910
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