150W MOSFET Amplifier with IRFP250x2

C3 and R5 are part of a pole-zero compensation system.

The advantage of pole-zero compensation is higher open loop gain at mid-high frequencies, which translates into lower high-frequency distortion and lower output impedance, without any substantial degradation in stability. The usual rise in output impedance and distortion above 1khz in traditional amplifiers is moved upwards, it does not start until a higher frequency (may be as high as 20khz resulting in flat THD and constant damping factor, which makes the amplifier closer to "ideal").

Pole-zero compensation is rarely used in DIY amplifiers because it's a bit more complex than the traditional dominant pole compensation and harder to implement for people with no knowledge about feedback control loop theory (or even without an oscilloscope).
Would you comment auto-bias circuit from post #53 ?
Regards
 
I should study it further because at first glance I don't see how it works. There are some node names on the schematic that are very hard to read, so I don't know where are the signals coming from. A higher quality picture or pdf would help.
Picture is high quality, use full screen when increase picture (click on four arows down in left corner).
Regards
 
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Bias is controlled through pulse width modulation.

The current flowing through the lower MOSFET is compared against a reference, which is desired bias level. It works much in the same way as a switching amplifier.

When current is below desired bias level, pwm (logic) output is on (high), otherwise it's off (low). The PWM output is lowpass filtered with a pole in the origin (like a servo) and the resulting (nearly DC) voltage is converted into current and fed to the optocoupler, which does the level shifting and sinks a proportional current from the base of the Vbe multiplier, which results in increased output stage bias.

So the more time the current through the lower MOSFET is below the desired bias level, the more bias voltage is applied to the gates of output transistors. In other words, the circuit tries to keep the lower MOSFET always biased.

I have seen this biasing scheme before, but implemented in another way. See Visch output stage (1975):

http://www.diyaudio.com/forums/solid-state/160285-class-b-w-o-crossover-distortion-1975-a.html
 
Bias is controlled through pulse width modulation.

The current flowing through the lower MOSFET is compared against a reference, which is desired bias level. It works much in the same way as a switching amplifier.

When current is below desired bias level, pwm (logic) output is on (high), otherwise it's off (low). The PWM output is lowpass filtered with a pole in the origin (like a servo) and the resulting (nearly DC) voltage is converted into current and fed to the optocoupler, which does the level shifting and sinks a proportional current from the base of the Vbe multiplier, which results in increased output stage bias.

So the more time the current through the lower MOSFET is below the desired bias level, the more bias voltage is applied to the gates of output transistors. In other words, the circuit tries to keep the lower MOSFET always biased.

I have seen this biasing scheme before, but implemented in another way. See Visch output stage (1975):

http://www.diyaudio.com/forums/solid-state/160285-class-b-w-o-crossover-distortion-1975-a.html
Thanks, what do you think about adding more outputs in parallel and increase rail voltage to get more power with this schematics?
Regards
 
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Nx14

NMOS amplifier based on Ultimate Fidelity Amplifier
 

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OK, thats quite low for a FET. Lateral FETS usually need 150mA and Vertical FETS are run at 400mA. If you look at the transfer characteristics in fig 3 on the link: http://www.datasheetcatalog.org/datasheet/irf/irfp250.pdf

You can see if you ran it at 400mA there is chance of thermal runaway.

I usually run mine at approx. 35mA and dont get any crossover distortion.

It is easy to get into thermal runaway with large bias currents unless there is thermal feedback.
 
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