Zen -> Cen -> Sen, evolution of a minimalistic IV Converter

OK, finally I spotted the problem. Basically a Schrodinger cat problem. One return GND line was missing, so my measurement system was acting for it, so depending how I was connecting probes the thing was working or not. Once the connection was done in a solid way, everything went under control.

D.
 
Hi all here.

As i am fiddling with a new "old" AD1856 i just bought from diyinhk, i also would like to make my own i/v stage for omitting the buildin opamp.
AD1856 R2R Isolated nonoversampling NOS Audio DAC with FIFO reclock V2 - DIYINHK

This dac i bought uses two AD1856 dac chip's, and datasheet states the following specs, which i think is important in my case.

+-3V or +-1mA output capability and so forth.

Eventhrough i read the article several times, i still find it hard to figure out what i have to build, and if it's possible at all with this dac? -Also i cannot find in thread if it's possible to use with an regulated 18vdc psu instead of using batteries? (I actually have an diyaudio superregulator in drawer :))

About the transistors, i have a handfull of 2sj74bl, 2sk170gr, 2sk170bl, one 2sk389V and two 2sj109V.

Hoping that someone can guide me a little further thanks :)

Jesper.
 

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I have to replace my batteries. The old ones were 600 mAh but the new ones are 500 mAh. If I do not change Rch for the charging circuit I will then get C/33.3 instead of C/40 which is recommended. Anyone knows what effect that will have on the batteries? I am asking because it will take me a while to replace the resistors since my case is packed pretty tight so if it will not make a difference I would rather not do that.
 
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This variant of the SEN I-V uses the available and inexpensive SMD BF862 jfet cascoded by J111, 3 in parallel ... and since we are doing overkill, let's go all the way and mirror balanced I-V circuits.

View attachment 593934

I'm using SMD film 0.1uF bypass caps but use a really high quality resistor at R3 and R7 attached at the output... thoughts on layout?

View attachment 593938

View attachment 593935
View attachment 593936

There are holes to allow a small finned heatsink to be placed over the 12 JFET array on each side of the board and tied in place with a cord.

Following this comes a similarly mirrored SK filter using Wurcer's discrete OPA (BF862 with hybrid BJT cascode)...

@jborden
I have a few questions.
- Can this be used with the es9018 (BufIII)?
-If yes, then how would you handle the DC ofset. Like its done in post #1883? http://www.diyaudio.com/forums/digi...-evolution-minimalistic-iv-converter-189.html
-What is the purpose of R2 and R8?
 
- Can this be used with the es9018 (BufIII)?
-If yes, then how would you handle the DC ofset. Like its done in post #1883? http://www.diyaudio.com/forums/digi...-evolution-minimalistic-iv-converter-189.html
-What is the purpose of R2 and R8?

I haven't worked with the es9018 but would handle DC offset as described. If I redo the layout it would be easy to provide this as an option.
R4/R8 were there from testing -- I leave them out

I also leave out Civ because the next stage has an input C -- would be redundant for my purposes.

For the es9018 or different DACs the big difference would be number of parallel jFets based on ldss. EUVL has described this both in the article and in this thread.
 
impedance: 15k (see digital output section of signalyst dsc1)

dc offset: yes, the drains are tied to ground in my schematic (and the base SEN I-V).
Ground in the SEN (given its floating supply) is simply a 0v reference, but can be set as desired.

I'd recommend checking things in LTSpice :)
 
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