Many audiophiles like to change opamps and test/listen. The results vary of course. Existing circuit Z may make some IC amps worse in one case and better in another. Nice to be able to narrow the choices with some real engineering explanation.
But lets eliminate the easy ones -- like high input source Z and high C devices (fet not cascoded).
..
But lets eliminate the easy ones -- like high input source Z and high C devices (fet not cascoded).
..
Last edited:
Richard, you like to harp that others aren't reading the available documentation, but you've read the abundant, excellent document notes on the topic? E.g. http://www.ti.com/lit/an/slyt595/slyt595.pdf
Rolling opamps in an oscillator is still opamp rolling. Caveat emptor.
Demian,
Multi mode glass for that one. Runs over 1000'. I presume that the data gets corrupted by more than single bit errors when things start to sound bad. In theory it should mute for bad data and in the start up we had a bad fiber and that zone did go intermittent at a fairly high rate of on and off.
On the bench building it was when I looked at jitter and sound quality. Once working well on the bench the gizmos were built and tested. Probably a mistake to test with a FO attenuator rather than a spool of fiber. Field work was just go or no go.
System has been working for years. The user got clever and uses the second channel for a different time alignment. So left is announcer mode, right is end zone origin.
There is a copper and transformer back up.
I don't know what AES receiver is used in the amplifier but it did show some interesting quirks. But turning off the master clock does make things not sound the same. (Of course many users of that mixing console use a small battery operated plug in master clock to improve the sound quality. )
Multi mode glass for that one. Runs over 1000'. I presume that the data gets corrupted by more than single bit errors when things start to sound bad. In theory it should mute for bad data and in the start up we had a bad fiber and that zone did go intermittent at a fairly high rate of on and off.
On the bench building it was when I looked at jitter and sound quality. Once working well on the bench the gizmos were built and tested. Probably a mistake to test with a FO attenuator rather than a spool of fiber. Field work was just go or no go.
System has been working for years. The user got clever and uses the second channel for a different time alignment. So left is announcer mode, right is end zone origin.
There is a copper and transformer back up.
I don't know what AES receiver is used in the amplifier but it did show some interesting quirks. But turning off the master clock does make things not sound the same. (Of course many users of that mixing console use a small battery operated plug in master clock to improve the sound quality. )
Bill
No, I don’t have specific recordings to give as an example.
I have two 1TB external HDs with flac and wav files and I use a notebook to send data through USB cable to a USB to I2S converter and then to the DAC of my 2x4 MiniDSP (ADAU1701 chip).
My observation does not come from critical listening (and I haven’t done a controlled test yet so, maybe I shouldn’t have spoken) but I listen to a lot from these files everyday (mostly classic and opera) and I have done the 0 to 6 dB USB volume attenuation long term comparison a few times.
Occasionally with some files, the sound terns harsh.
Looking at the software Peak meters which show the input level of the DAC, the harshness coincides with peak values close to the FS. Turning the USB-out volume down (and complementary turning the DAC-out volume up) makes this harshness dissapear.
I have also a CD player (Rotel RCD 965BX) of which I use the digital out to feed the DAC. Rotel does not have a volume control and I hear that harshness there too with signals close to peak meters FS.
I can’t say exactly at which level the trouble starts because the sampling period for the peak meters is somewhere close to 1/2s and I lose accuracy.
Note that for the ADAU1701, the DAC out is specified for Total Harmonic Distortion + Noise −90 dB at −1 dB full-scale analog output.
I am very certain that my lousy ears need a lot more than –90dB of distortion to notice something wrong, thus my comment that "if I can hear it, everyone can hear it".
It’s good to do THD measurement using sinusoid input for to be more specific.
George
The low noise objective of the device dictates that the input bias currents are high. If your circuit cannot deal with that, then its not the right choice - use something else. For Rsource of about 500-1.5k I think the device is unbeatable, along with the very low distortion and hefty OPS.
The LME49710 is also very good - I never had any problems applying it either although some issues were raised a few months ago on this thread. The Ib on that device is typically 10nA which is very low for a bip input device.
The LME49710 is also very good - I never had any problems applying it either although some issues were raised a few months ago on this thread. The Ib on that device is typically 10nA which is very low for a bip input device.
Demian
BTY I think I have created a bit of confusion. The diffèrence between clock jitter and data jitter.
If you are clocking your D/A at 44,100 and want 16 bits of resolution then you would want the timing accuracy about twice that or 1/(44,100 x 2 x 65536) or 1.73e-10 or 17 nS peak jitter. Not to be confused with RMS numbers. (Now how often say 350 pS RMS yields more than 17 nS of jitter should be low.)
Now for data transmission we have the unit interval. The clock is recovered from the data rate and with a PLL and a bit of time can be recovered to at least that accuracy. But peak jitter of more than 1/2 UI can corrupt the data in transmission to more than a single bit error. Yes there are algorithms to try and do better.
Pretty sure (well certain) you know the difference not sure everyone follows.
BTY I think I have created a bit of confusion. The diffèrence between clock jitter and data jitter.
If you are clocking your D/A at 44,100 and want 16 bits of resolution then you would want the timing accuracy about twice that or 1/(44,100 x 2 x 65536) or 1.73e-10 or 17 nS peak jitter. Not to be confused with RMS numbers. (Now how often say 350 pS RMS yields more than 17 nS of jitter should be low.)
Now for data transmission we have the unit interval. The clock is recovered from the data rate and with a PLL and a bit of time can be recovered to at least that accuracy. But peak jitter of more than 1/2 UI can corrupt the data in transmission to more than a single bit error. Yes there are algorithms to try and do better.
Pretty sure (well certain) you know the difference not sure everyone follows.
Last edited:
That's incredibly low.
The datsheet shows max Ib of 72nA and max Ios of 65nA.
With a Darlington input pair and an hFE for the input devices at 1000, the Ie of that input device would be 72uA, indeed tiny!
Are there others that get that low?
Does the closeness of Ios to Ib tell us something about the biasing currents?
The datsheet shows max Ib of 72nA and max Ios of 65nA.
With a Darlington input pair and an hFE for the input devices at 1000, the Ie of that input device would be 72uA, indeed tiny!
Are there others that get that low?
Does the closeness of Ios to Ib tell us something about the biasing currents?
George, maybe this old article will give you a hint on what's going on:
Jitter - Digital Domain: CD Mastering | Mastered for iTunes | Audio Mastering | Blu-Ray Mastering
Best,
I am asking what it is about the 797 which would make its thd higher than others with the Z used for osc of the 339A. Seems like a simple enough question for the principal designer. Something in its input topology? Feedback elements values?
THx-RNMarsh
Last edited:
Try balancing the Z at all frequencies, i.e. DO design. Did wonders for the FET amps folks like to bash for common mode linearity.
I cant read the faint letters. CM issues?
Balancing the Z would improve the CM conditions for 797.
-RM
Last edited:
Last edited:
I'll also remind you that before Bateman, before LT, etc. Jeff Smith and I published a .1ppm oscillator article.
John maybe you should ask Bruce Hofer at AP how he "manages" to get it to work.
Attachments
Looking at the actual oscillator schematic of the HP339, I cam see where the AD797 is not the best fit. You apparently have to avoid some circuit configurations, because the AD797, as good as it is generally, has input impedance issues. Scott, this is called upgrading, not re-design. We can't tear apart the HP339 completely to make your IC work optimally. Other IC's apparently work better in this circuit. Was that the LT part, Richard that you found worked best?
Richard, I see what your problem is. To get it right, get the original PDF from Samuel Groner on the internet where he measures a number of IC's for distortion. Hunt around and you will find it. It is over 200pages, I think.
The problem is nonlinear input impedance with frequency, or some-such.
The problem is nonlinear input impedance with frequency, or some-such.
- Status
- Not open for further replies.