It is a good point - there is really no one right way to do it.
It depends on what you are trying to accomplish and how you want to do it.For instance one of the design goals of IVY-III was capability to drive balanced headphones directly - which it does very well.
Still I have experimented with dozens of output ideas for the ES9018 - and I can say there are many ways to get excellent results.
It is a good point - there is really no one right way to do it.
For instance one of the design goals of IVY-III was capability to drive balanced headphones directly - which it does very well.
Still I have experimented with dozens of output ideas for the ES9018 - and I can say there are many ways to get excellent results.
I've been listening to music produced by BIII DAC in sync mode with SDtrans, and the output stage showed above, for more than e year and I don't feel any need to experiment with other setups ;-)
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I want to try:
L1-2 are 1mH?
2SK117 grade: Y, Gr or BL? any recommended Idss?
BF862 matched? any recommended Idss?
2SA1837 matched? HFE or other characteristic?
TIA
Felipe
Yes
BL, but does not matter to much ;-)
Yes, more than 10mA
Yes, HFE
Note: In order to cancel even harmonics it is very important to match as close as possible every symmetrical components. If everything is correctly matched, including resistors and inductance, you will have a very low offset, 1...2mV
1..2mV is low offset now?.. I'm having 0.15mV (in worst case, cold amp) on my speaker terminals and keep worrying how to extinguish this.
Can you please explain the idea of your sketch? It looks much worse than classical virtual-ground schematics from ESS datasheet, and gives no visible advantages over voltage-mode output. But it does require tight matching of those components.
Thanks for understanding.
Do you have to build a high power instrumental amplifier? IMHO, few mV offset are irrelevant for a exceptional sounding audio amplifier.
The idea behind the sketch? Well, this is not a I/V stage, it is just a low pass filter and a unity gain buffer.
Well, magnetizing a midwoofer by tens of mV adds percents of distortions exponentially, so my idea is to move as close to zero as possible. Not an instrumental amp, moreover, noFB one.
Buffer and filter, yes. But why not just a follower before (and after) a passive RC?
Just a simple RC filter is not enough. To much noise after the DAC.
I listen to this output stage since last year and is perfect, at least for me
I agree completely. I am running my in a sort of similar configuration. Difference being is that I am using buffer to interface DAC and with Lundahl audio transformer after buffer, that serves several roles - voltage amplification, DC blocking and low pass filter. Very transparent.
I think maybe some members here it may find interesting some of the ESS DAC (never done before) measurements and results published here:
https://www.youtube.com/watch?v=2QySxRcuPJs
Well, there is not so much to see in this video about the measurements environment, as many other details. But I think that now, as the first step is done, another people will may repeat these measurements...
However, some doubts are now switched on in this field...
There are few main conclusions/results out of these measurements:
- The ES9018 it have serious problems (its analogue outputted result) when to work over 20bit resolution.
- The same DAC chip it lose the precision and linearity at higher sampling frequencies (over 48Khz). This finding it may explain somehow why ES9018 it may sound better (for someone... ), at higher clock frequencies...
- The ESS DAC is behind AKM and PCM17xx families, in few of the performances areas.
We may just let the time to confirm or not the doubts about this so far well appreciated ESS DAC chip.
https://www.youtube.com/watch?v=2QySxRcuPJs
Well, there is not so much to see in this video about the measurements environment, as many other details. But I think that now, as the first step is done, another people will may repeat these measurements...
However, some doubts are now switched on in this field...
There are few main conclusions/results out of these measurements:
- The ES9018 it have serious problems (its analogue outputted result) when to work over 20bit resolution.
- The same DAC chip it lose the precision and linearity at higher sampling frequencies (over 48Khz). This finding it may explain somehow why ES9018 it may sound better (for someone... ), at higher clock frequencies...
- The ESS DAC is behind AKM and PCM17xx families, in few of the performances areas.
We may just let the time to confirm or not the doubts about this so far well appreciated ESS DAC chip.
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It would be great to have an English translation somehow. Particularly when he explains measurement set up. Sure one could put dots together but still... Thank you for posting.
His other videos also looks very insightful.
eg. this video https://www.youtube.com/watch?v=vnzK-l18a7c
It looks he explains why ES9018's AVCC supply affect its performance and shows measurement result.
I hope if he came this forum and gave us some his wisdom.
and I found his blog https://jipihorn.wordpress.com/
eg. this video https://www.youtube.com/watch?v=vnzK-l18a7c
It looks he explains why ES9018's AVCC supply affect its performance and shows measurement result.
I hope if he came this forum and gave us some his wisdom.
and I found his blog https://jipihorn.wordpress.com/
In the video in your link he pointed out at least on two basic characteristic of ESS DACs:
The absolute immunity of the device to the clock jitter (he named an experiment about altering the clock signal especially to measure the DAC performances in this area).
The impact of power sources for the DAC voltage reference stage.
We do not know yet exactly if ES9018 and its internal reference system is powered by AVCC, and how is working, but as this chip is so sensible at the quality of its AVCC rail, it seems to be true that this rail it may power a reference system, among some other key stages...
Fully agree, the contribution of this guy to this forum can be very significant...
The absolute immunity of the device to the clock jitter (he named an experiment about altering the clock signal especially to measure the DAC performances in this area).
The impact of power sources for the DAC voltage reference stage.
We do not know yet exactly if ES9018 and its internal reference system is powered by AVCC, and how is working, but as this chip is so sensible at the quality of its AVCC rail, it seems to be true that this rail it may power a reference system, among some other key stages...
Fully agree, the contribution of this guy to this forum can be very significant...
I don't agree with this. Not so much immunity from the audiophile point of listening.
I convince the schematic on this post illustrates the possible DA stage of Sabre32 architecture in the most accurate manner so far.
http://www.diyaudio.com/forums/digital-line-level/117238-ess-sabre-reference-dac-8-channel-226.html#post3521975
I think the AVCC power supply should be regarded not as a voltage reference but a current source.
I'd like to do a translation of the video for you guys but that would take too much time.
So, the test you're talkng about is to output square wave with exponentially decreasing amplitude, so you can see it sinking in the noise floor, so you know where the noise floor is.
It seems the AKM gets better with higher sample rate. Since it gets its MCLK from the SPDIF receiver, faster sample rate means faster clock, which for a sigma delta means it can output at a higher rate, which translates to better SNR.
My opinion : If you're in a grumpy mood, you could say that the AKM gets worse at lower sample rates, because it has to use the clock that is given to it.
It seems the ESS gets worse with higher sample rate. You could also say it gets better with lower sample rate, because unlike the AKM, it doesn't give a damn about the incoming MCLK and the modulator always runs at the local MCLK rate.
Also it seems that when he uses a higher sample rate, the test signal also gets faster.
> We do not know yet exactly if ES9018 and its internal reference system
> is powered by AVCC, and how is working,
Actually yes we do. It's very simple. Like all other DACs, the output is the multiplication of the reference with the digital sample value. In ES9018 there is no internal reference system. AVCC is the reference.
So, the test you're talkng about is to output square wave with exponentially decreasing amplitude, so you can see it sinking in the noise floor, so you know where the noise floor is.
It seems the AKM gets better with higher sample rate. Since it gets its MCLK from the SPDIF receiver, faster sample rate means faster clock, which for a sigma delta means it can output at a higher rate, which translates to better SNR.
My opinion : If you're in a grumpy mood, you could say that the AKM gets worse at lower sample rates, because it has to use the clock that is given to it.
It seems the ESS gets worse with higher sample rate. You could also say it gets better with lower sample rate, because unlike the AKM, it doesn't give a damn about the incoming MCLK and the modulator always runs at the local MCLK rate.
Also it seems that when he uses a higher sample rate, the test signal also gets faster.
> We do not know yet exactly if ES9018 and its internal reference system
> is powered by AVCC, and how is working,
Actually yes we do. It's very simple. Like all other DACs, the output is the multiplication of the reference with the digital sample value. In ES9018 there is no internal reference system. AVCC is the reference.