I am working on the layout today. I found out that the L1 chip was just not going to be able to handle what I wanted to do, so I switched to the L2. Otherwise it would be ready for protos by now.
So the L2 is a dual core?
A question for i2s masters...
If one used this usb-interface as master, does all slaves synchronize perfectly automatically?
What I wonder is if it would work fine to have both i2s and spdif output at the same time, spdif to an external flashy DAC but i2s to an Opus for subwoofer output.
Would both these DACs be perfectly synchronized without me having to do anything other than connect them correctly?
Or would multiple DACs complicate matters such that it would be better to skip the subwoofer dedicated Opus and instead use flashy dac output -> lowpass and then combine the for the subwoofer.
// Olle
If one used this usb-interface as master, does all slaves synchronize perfectly automatically?
What I wonder is if it would work fine to have both i2s and spdif output at the same time, spdif to an external flashy DAC but i2s to an Opus for subwoofer output.
Would both these DACs be perfectly synchronized without me having to do anything other than connect them correctly?
Or would multiple DACs complicate matters such that it would be better to skip the subwoofer dedicated Opus and instead use flashy dac output -> lowpass and then combine the for the subwoofer.
// Olle
Not alot happening here.. what's the status? I need it badly for my BII project..
Since I switched from L1 to L2 device I am just being extra careful verifying things because it is not an "app note" design. I am charting a new path for this device.
I have the layout mostly done, I am just working with XMOS and other to verify my work before I start to consume parts.
So yes there is progress.
Also please note there here are TPA we have several new modules in the works which we are extremely excited about. This is only one of those.
Cheers!
Russ
Since I switched from L1 to L2 device I am just being extra careful verifying things because it is not an "app note" design. I am charting a new path for this device.
I have the layout mostly done, I am just working with XMOS and other to verify my work before I start to consume parts.
So yes there is progress.
Also please note there here are TPA we have several new modules in the works which we are extremely excited about. This is only one of those.
Cheers!
Russ
Russ,
I hope i didn't seem ungrateful - i just feared that this would become postponed much more than it has. I see it's been set for November '10.. i don't mind waiting for quality, but a guy has to know when he can get his new toys
In your testing, have you been able to obtain 32 bit or is it "only" 24 bit? - i'm not going to take advantage of it, but i'm just really interested in the project.
I2S RJ45 connector
Russ,
As the USB transport is also a very interesting "stand-alone" module for people to use between PC and DAC I was wondering if you could accommodate pads for a RJ45 connector for the I2S out using the same pinning as the (few) commercial DAC's that have I2S input (like North Star). And for those (few) of us already tapping DSD/I2S from SACD-players and sending it to the Buffalo using the CAT5/RJ45 interface.
Cheers,
Nic
Russ,
As the USB transport is also a very interesting "stand-alone" module for people to use between PC and DAC I was wondering if you could accommodate pads for a RJ45 connector for the I2S out using the same pinning as the (few) commercial DAC's that have I2S input (like North Star). And for those (few) of us already tapping DSD/I2S from SACD-players and sending it to the Buffalo using the CAT5/RJ45 interface.
Cheers,
Nic
Hows the windows 7 support looking now? If I remember there were some issues regarding this.
Also will there be indicators (LEDs/output pins etc) anywhere that will show the sample rate? I'm going to want some kind of indicator that I can input into a microcontroller for system changes based on sampling frequency and something like that would be very useful.
Also what clock(ing scheme) will be used for the output?/What kind of jitter performance will this have? I expect this to be good anyway, I'm just curious I think lots of people are eagerly awaiting this project! And I just noticed this thread too.
Also will there be indicators (LEDs/output pins etc) anywhere that will show the sample rate? I'm going to want some kind of indicator that I can input into a microcontroller for system changes based on sampling frequency and something like that would be very useful.
Also what clock(ing scheme) will be used for the output?/What kind of jitter performance will this have? I expect this to be good anyway, I'm just curious I think lots of people are eagerly awaiting this project! And I just noticed this thread too.
What about Thunderbolt?
Simply no need for that kind of bandwidth here.
Simply no need for that kind of bandwidth here.
The optical version will have galvanic isolation and the DAC can be 100 meters from the computer. Probably something for the future when it replaces firewire etc.
Russ, great project! If the I8S and ASIO work out it'll be really sweet---getting 1394 into a fanless PC to thunk through a couple Firewire audio interfaces to get enough SPDIF outs to run a triamp or quadamp is really kind of a hassle. (The xmon parts seem to be the next best thing to audio SHARCs but they lack the SRAM to support time reversed IIR. And VisualDSP++ for the SHARCs starts at USD 3.6k. So I'm kind of locked in to a PC crossover for the time being.)
Thunderbolt only supports the PCIe and mDP protocols. It's very much a dumbed down version of what initially was promised.What about Thunderbolt?
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