Hi Samuel,
This is a good point. I think one can also just put a DC source on the input of the amplifier if it is DC coupled, at the same time loading the amplifier with a resistive or reactive load to obtain the desired combination of voltage and current.
This can also be done to a real amplifier; in fact in that case the operating point can be moved by a low-frequency sinusoidal input at, say, 20Hz. The higher-frequency small-signal test tone or square wave can then be added to the input signal. The low-frequency tone can be filtered out at the output with a suitable HPF so that one can then see the test tone at the output.
One could further backfeed the amplifier through a load resistor with a second LF tone at, say, 19Hz, to exercise many combinations of voltage and current. Such a test needs to be carried out with caution, however.
Cheers,
Bob
http://focus.ti.com/lit/ds/symlink/tps7a4901.pdf
Yes, that does look more promising than their other recent offerings which include a high frequency charge pump on chip.
Yes, that does look more promising than their other recent offerings which include a high frequency charge pump on chip.
Hi Godfrey,
This is a really nice piece of investigative work, and the results are portrayed well. We should all bear in mind that these kinds of tests are very useful for real amplifiers - not just in simulation.
What power transistor models were you using?
Yes, ft droop can be a big problem with power transistors, even with many of the fast ring-emitter/perforated-emitter devices. For numerous reasons, it always seems wise to err on the side of more paralleled output devices.
However, it is always important to bear in mind that more paralleled devices means more capacitance to drive for the driver (and that that capacitance can increase dramatically when the output voltage is near the rails). Although it seems wasteful of power supply resources, it is also often wise to use Baker clamps or something similar to prevent the output transistor bases from ever getting closer than, say, 5V from the rails. Those extra couple of watts you get by letting the output transistors get really close to the rails can extract a penalty (not to mention increased vulnerability to ripple on the rail feeding through upon clipping).
Cheers,
Bob
Spice models and simulations
Bob,
I'm enjoying your book; at least what I've read so far. I've also downloaded your spice simulations and want to thank you for sharing this work. My question is about the use and modification of the simulations. Using your simulations as a baseline, I've been changing the output configuration and re-running the simulations in comparison to the baseline. I would like to put my results up on this forum, with credit to you and disclaimers where I have changed the simulations. Is this ok with you?
Again thank you for all of your contributions and help this neophyte.
Regards,
Ken
Bob,
I'm enjoying your book; at least what I've read so far. I've also downloaded your spice simulations and want to thank you for sharing this work. My question is about the use and modification of the simulations. Using your simulations as a baseline, I've been changing the output configuration and re-running the simulations in comparison to the baseline. I would like to put my results up on this forum, with credit to you and disclaimers where I have changed the simulations. Is this ok with you?
Again thank you for all of your contributions and help this neophyte.
Regards,
Ken
Hi Ken,
Thanks for buying my book and I'm happy that you're enjoying it. I'm glad you've been able to use the simulations and models from my website, and I do plan to put up more models and simulations in the near future.
By all means it is fine with me to put your results up on the forum for others to see.
Cheers,
Bob
Hi Olivier,
I'm sorry I did not get back to you sooner on your question. I'm a little skeptical that the problem is the length or layout of that PCB trace, but it is true that there are a lot of potential sources of capacitance hanging on that node. I'm not an expert on CMCL, and so don't know what role if any it is playing here. As you know, I use a different approach in my book to cure the fighting VAS problem in this topology.
Are you using two Miller comp capacitors, each from output to input of the VAS? If the design is such that their value is small (e.g., less than, say, 30 pF), then a large amount of stray capacitance hanging on the VAS input node might bother the circuit. Do these concerns show up in simulation or just in a real amplifier?
Cheers,
Bob
Hi Bob
Thanks for the feedback
I just used LTSpice to run the .asc file extracted from the zip file you supplied, then added another pair of the same output devices already used.
Checking now, I see there's an include command, so presumably it used the MJL21193C/MJL21194C models from your text file.
The real shocker was the amplitude and waveforms of the drivers' base currents with high frequency high power output - much worse than expected.
It's quite astonishing how badly mangled the internal waveforms have to be to achieve a clean output from a class AB amp under those conditions.
OTOH, if you start with the idea of building a 50 watt amp, it just means you'll have to use a slightly bigger transformer (maybe 28-0-28) and a little extra heatsink, for negligible extra cost.
I think the awkward bit is ensuring that the rail voltage never dips below the clip voltage, which means giving extra attention to psu droop etc. Ideally it would be nice to clip at a fixed voltage but that's probably not practical due to uncertainty regarding the line voltage (and hence rail voltage).
Do you set the clip voltage relative to the rail voltage (e.g. 90% of rail, or rail - 5V), and then just filter it to get rid of ripple? If so, what sort of time constant would you recommend?
My concern is that we want to effectively filter the 100/120Hz ripple, but don't want VLF variations to be attenuated or badly phase shifted. e.g. When playing loud 90bpm music, the rail voltage will be varying at 1.5 Hz and, depending on house wiring, the line voltage can also suddenly drop when other power-hungry appliances are switched on.
Cheers - Godfrey
Thanks for the feedback
I'm not quite sure
I just used LTSpice to run the .asc file extracted from the zip file you supplied, then added another pair of the same output devices already used.Checking now, I see there's an include command, so presumably it used the MJL21193C/MJL21194C models from your text file.
I was surprised recently, when poking about the internal workings of an amp sim, to find that 2 pairs of thermaltrak output devices presented a load of almost 1nF to the driver stage, with no load on the output. A quick look at the datasheets confirmed your models got that about right.
The real shocker was the amplitude and waveforms of the drivers' base currents with high frequency high power output - much worse than expected.
It's quite astonishing how badly mangled the internal waveforms have to be to achieve a clean output from a class AB amp under those conditions.
Interesting ideas there. How bad the penalty is depends on how you look at it. If you start with the intent to use a 25-0-25 mains transformer, it could mean 35 instead of 50 watts output, and seem like a really bad idea.
OTOH, if you start with the idea of building a 50 watt amp, it just means you'll have to use a slightly bigger transformer (maybe 28-0-28) and a little extra heatsink, for negligible extra cost.
I think the awkward bit is ensuring that the rail voltage never dips below the clip voltage, which means giving extra attention to psu droop etc. Ideally it would be nice to clip at a fixed voltage but that's probably not practical due to uncertainty regarding the line voltage (and hence rail voltage).
Do you set the clip voltage relative to the rail voltage (e.g. 90% of rail, or rail - 5V), and then just filter it to get rid of ripple? If so, what sort of time constant would you recommend?
My concern is that we want to effectively filter the 100/120Hz ripple, but don't want VLF variations to be attenuated or badly phase shifted. e.g. When playing loud 90bpm music, the rail voltage will be varying at 1.5 Hz and, depending on house wiring, the line voltage can also suddenly drop when other power-hungry appliances are switched on.
Cheers - Godfrey
Thermaltrak stability
Hello Bob,
I would appriciate your comment on ThermalTrak+TMC tread.
I tried to follow your advice how to implement a bias current stability and if you can take a look to this tread.
http://www.diyaudio.com/forums/solid-state/182554-thermaltrak-tmc-amp.html
thank you in advance
Damir
Hello Bob,
I would appriciate your comment on ThermalTrak+TMC tread.
I tried to follow your advice how to implement a bias current stability and if you can take a look to this tread.
http://www.diyaudio.com/forums/solid-state/182554-thermaltrak-tmc-amp.html
thank you in advance
Damir
Hi Olivier
You might be interested in an alternative approach I showed in this thread: http://www.diyaudio.com/forums/solid-state/180448-fresh-fix-slone-amp-ie-yet-another-symetric-topology.html Since I don't have Bob's book yet, I'm not sure if it's the same as his approach or not.
FWIW, I think you really got suckered with that design, purely from a complexity point of view. Whenever I see a design with about 100 more transistors than strictly needed, my knee-jerk reaction is:"Well, I'm certainly not going to solder all of that". Sorry to say but I'm too lazy to even try figure out how it's supposed to work. Perhaps you haven't been getting much help because other forum members feel the same way?
Unfortunately Edmond seems to have abandoned diyAudio, so you're kinda stuck with it.
[ot] I hope Edmond's OK. I'm starting to miss the resident Mr Grumpy.
[/ot]CMCL
Hi Bob,
No problem to take time to react. In simulation the amp with it's CMCL approach performs very well. In reality, the DC part is perfectly matched with the simulation. The fighting issue seems solved. But it's AC behavior is not so clean. My first concern is the Bode Plot. I placed my measurements on top of the AC simulation sheet. It is uploaded in my own thread as it is a bit off base in this thread which is about your book in general...
As for the miller caps, they are indeed between 20 and 30 pF from output VAS to input VAS. I still have 2 other PCB's which I can solder to see if it behaves equally. Maybe there is a dog in my first pcb (production error or solder spatter, or .... pics are also in my thread for who is interested).
Indeed I read your solution for the fighting VAS with interest. If I cannot tame the CMCL I will certainly do some simulation with it ... but I want to give the CMCL a little more of my time ... however time starts to be a concern ... I will be dady within 2 or 3 weeks
Hi Godfrey,
Thanks for your input. I will check it out tonight too. Let's see if it's the same as in Bob's book. Indeed I am using Edmonds help here ...
Till later guys,
Cheers,
Olivier
Hi Bob,
No problem to take time to react. In simulation the amp with it's CMCL approach performs very well. In reality, the DC part is perfectly matched with the simulation. The fighting issue seems solved. But it's AC behavior is not so clean. My first concern is the Bode Plot. I placed my measurements on top of the AC simulation sheet. It is uploaded in my own thread as it is a bit off base in this thread which is about your book in general...
As for the miller caps, they are indeed between 20 and 30 pF from output VAS to input VAS. I still have 2 other PCB's which I can solder to see if it behaves equally. Maybe there is a dog in my first pcb (production error or solder spatter, or .... pics are also in my thread for who is interested).
Indeed I read your solution for the fighting VAS with interest. If I cannot tame the CMCL I will certainly do some simulation with it ... but I want to give the CMCL a little more of my time ... however time starts to be a concern ... I will be dady within 2 or 3 weeks
Hi Godfrey,
Thanks for your input. I will check it out tonight too. Let's see if it's the same as in Bob's book. Indeed I am using Edmonds help here ...
Till later guys,
Cheers,
Olivier
Hi Bob
Thanks for the feedback
I'm not quite sure
Checking now, I see there's an include command, so presumably it used the MJL21193C/MJL21194C models from your text file.
I was surprised recently, when poking about the internal workings of an amp sim, to find that 2 pairs of thermaltrak output devices presented a load of almost 1nF to the driver stage, with no load on the output. A quick look at the datasheets confirmed your models got that about right.
The real shocker was the amplitude and waveforms of the drivers' base currents with high frequency high power output - much worse than expected.
It's quite astonishing how badly mangled the internal waveforms have to be to achieve a clean output from a class AB amp under those conditions.
Interesting ideas there. How bad the penalty is depends on how you look at it. If you start with the intent to use a 25-0-25 mains transformer, it could mean 35 instead of 50 watts output, and seem like a really bad idea.
OTOH, if you start with the idea of building a 50 watt amp, it just means you'll have to use a slightly bigger transformer (maybe 28-0-28) and a little extra heatsink, for negligible extra cost.
I think the awkward bit is ensuring that the rail voltage never dips below the clip voltage, which means giving extra attention to psu droop etc. Ideally it would be nice to clip at a fixed voltage but that's probably not practical due to uncertainty regarding the line voltage (and hence rail voltage).
Do you set the clip voltage relative to the rail voltage (e.g. 90% of rail, or rail - 5V), and then just filter it to get rid of ripple? If so, what sort of time constant would you recommend?
My concern is that we want to effectively filter the 100/120Hz ripple, but don't want VLF variations to be attenuated or badly phase shifted. e.g. When playing loud 90bpm music, the rail voltage will be varying at 1.5 Hz and, depending on house wiring, the line voltage can also suddenly drop when other power-hungry appliances are switched on.
Cheers - Godfrey
You're quite right about the load presented to the driver by the collector-base capacitance of the output transistors, especially when Vcb is less than about 10V. People have complained about the drain-gate capacitance in power MOSFETs quite rightly so, but it is a problem with BJTs that can be on the same order of magnitude in some cases.
Also right about the distorted waveform that can often be seen in the drive circuit to the output transistor at high levels at high frequencies. This often has to do with the combination of charge storage in the base of the output transistor and the needed drive current for the collector-base capacitance. I often look at the collector current waveform of the driver, which, in a class A driver like that in the Locanthi output Triple, should never go to zero. Running the drivers at a higher bias current helps. I discuss this in the output stage chapter in my book.
I usually reference the Baker clamps to the rail voltage that is supplying the VAS. This rail voltage should be filtered with respect to the main rail voltage that supplies the output stage. It will react quickly enough, but will filter out the worst of the power supply ripple and noise. In better designs, I like to go through R-C filters on the rails as the rail voltage progresses back from the main rail voltage to the driver, to the pre-driver, and to the VAS. Even though the series resistors in these filters should be small (1-10 ohms), the progressive filtering isolates the stages at high frequencies, damps the rails, and reduces power supply noise. If desired, it is certainly not unreasonable to pass the VAS rail voltage through one more R-C filter before it is used as the Baker clamp reference.
As far as the price to be paid for limiting swing so that the output transistors do not get too close to the rail, I view this as just a couple of more volts needed on the rail voltage, regardless of the power rating of the amplifier.
Cheers,
Bob
Hi Damir,
I have not been following that thread, so I'm not quite sure what your question is. A skim of the thread looks like you have been successful. Is there a specific problem that you need advice on?
Cheers,
Bob
Hi Bob,
I followed all what was written on ThermalTrak theme in this forum, specially what you have been writing abouth it. I separated Vbe multiplier from main heatsink and thermally connected with a drivers only. I tried to simulate thermal stability, but I am not sure in result.
I did a bit of the real life test, connected amp to +-30V power supply (it was designed for +-50V). The bias current increased a bit with temperature, from 130mA at 25 degree C to 150-160mA at 50 degree C per output pair. There was no thermal runaway but there is a space for improvement and I do not have idea how. Maybe you can suggest what to change in the schematic.
thank you for your time
Damir
I followed all what was written on ThermalTrak theme in this forum, specially what you have been writing abouth it. I separated Vbe multiplier from main heatsink and thermally connected with a drivers only. I tried to simulate thermal stability, but I am not sure in result.
I did a bit of the real life test, connected amp to +-30V power supply (it was designed for +-50V). The bias current increased a bit with temperature, from 130mA at 25 degree C to 150-160mA at 50 degree C per output pair. There was no thermal runaway but there is a space for improvement and I do not have idea how. Maybe you can suggest what to change in the schematic.
thank you for your time
Damir
Hi Bob,
No problem to take time to react. In simulation the amp with it's CMCL approach performs very well. In reality, the DC part is perfectly matched with the simulation. The fighting issue seems solved. But it's AC behavior is not so clean. My first concern is the Bode Plot. I placed my measurements on top of the AC simulation sheet. It is uploaded in my own thread as it is a bit off base in this thread which is about your book in general...
As for the miller caps, they are indeed between 20 and 30 pF from output VAS to input VAS. I still have 2 other PCB's which I can solder to see if it behaves equally. Maybe there is a dog in my first pcb (production error or solder spatter, or .... pics are also in my thread for who is interested).
Indeed I read your solution for the fighting VAS with interest. If I cannot tame the CMCL I will certainly do some simulation with it ... but I want to give the CMCL a little more of my time ... however time starts to be a concern ... I will be dady within 2 or 3 weeks
Hi Godfrey,
Thanks for your input. I will check it out tonight too. Let's see if it's the same as in Bob's book. Indeed I am using Edmonds help here ...
Till later guys,
Cheers,
Olivier
Hi Olivier,
The AC behavior and the Bode plot you are unhappy with, are they in simulation or in the real world?
If in the real world, how did you measure the response to obtain the Bode plot?
Although you like the CMCL, you may want to separate the issues in the AC behavior by at least temporarily taking out the CMCL and use a simpler, different way of stabilizing the DC against the fighting.
Cheers,
Bob
Bode Plot
Hi Bob,
Hereby the AC bode plot. The red line is the simulated bode plot in microcap. The blue dots and line (+values) are the one measured on the pcb. Using this method : amp input to ground, input signal of the generator at the input of the feedback network while establishing the DC part with a resistor connected between amp output (in my case vas output) and the point between the resistor and the capacitor of the feedback network.
The problem is that the phase is rolling off much faster as the simulated one. Around 2MHz the phase margin starts to rise again to intercept the simulated line (almost), right after that I crashes down again.
I am puzzled of this behavior !?
I must say that measurement results above 1Mhz becomes very shaky ...
Hopefully this helps understanding...
Cheers
Olivier
Hi Bob,
Hereby the AC bode plot. The red line is the simulated bode plot in microcap. The blue dots and line (+values) are the one measured on the pcb. Using this method : amp input to ground, input signal of the generator at the input of the feedback network while establishing the DC part with a resistor connected between amp output (in my case vas output) and the point between the resistor and the capacitor of the feedback network.
The problem is that the phase is rolling off much faster as the simulated one. Around 2MHz the phase margin starts to rise again to intercept the simulated line (almost), right after that I crashes down again.
I am puzzled of this behavior !?
I must say that measurement results above 1Mhz becomes very shaky ...
Hopefully this helps understanding...
Cheers
Olivier
Hi Oliver,
How much of this effect is caused by the insertion of the generator?
Maybe Bob can shed some light on this. Is the generator transformer coupled and if it is won't that add some inductance to the equation?
David.
Hi Damir,
I think you really need to read the material in my book on the application of ThermalTrak transistors and the various kinds of bias spreaders to use with them, and how to adjust the temperature compensation balance between the driver transistors and the output transistors. There is simply not enough coherent detail in the thread to cover this well.
I also note that you are not using a Triple in the output stage; you can do a lot better in sound quality if you use a Triple.
Cheers,
Bob