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Better power MOSFET models in LTSpice
Better power MOSFET models in LTSpice
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Old 2nd April 2019, 06:16 AM   #211
aparatusonitus is offline aparatusonitus  Croatia
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Quote:
Originally Posted by Cartman222 View Post
Does anyone have an LTspice model for an IRF730 n-Channel Power MOSFET?
.SUBCKT IRF730 1 2 3
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
* Model generated on Sep 8, 97
* MODEL FORMAT: SPICE3
* Symmetry POWER MOS Model (Version 1.0)
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
M1 9 7 8 8 MM L=100u W=100u
* Default values used in MM:
* The voltage-dependent capacitances are
* not included. Other default values are:
* RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
.MODEL MM NMOS LEVEL=1 IS=1e-32
+VTO=4.08133 LAMBDA=0.00196769 KP=3.10024
+CGSO=6.36039e-06 CGDO=1e-11
RS 8 3 0.0677475
D1 3 1 MD
.MODEL MD D IS=6.91304e-09 RS=0.0167032 N=1.5 BV=400
+IBV=0.0001 EG=1.2 XTI=2.71224 TT=0
+CJO=6.68134e-10 VJ=3.03288 M=0.851335 FC=0.5
RDS 3 1 2e+07
RD 9 1 0.731541
RG 2 7 4.31009
D2 4 5 MD1
* Default values used in MD1:
* RS=0 EG=1.11 XTI=3.0 TT=0
* BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50
+CJO=1.03652e-09 VJ=1.39088 M=0.9 FC=1e-08
D3 0 5 MD2
* Default values used in MD2:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* BV=infinite IBV=1mA
.MODEL MD2 D IS=1e-10 N=0.535061 RS=3e-06
RL 5 10 1
FI2 7 9 VFI2 -1
VFI2 4 0 0
EV16 10 0 9 7 1
CAP 11 10 1.03652e-09
FI1 7 9 VFI1 -1
VFI1 11 6 0
RCAP 6 10 1
D4 0 6 MD3
* Default values used in MD3:
* EG=1.11 XTI=3.0 TT=0 CJO=0
* RS=0 BV=infinite IBV=1mA
.MODEL MD3 D IS=1e-10 N=0.535061
.ENDS irf730
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Old 2nd April 2019, 06:19 AM   #212
aparatusonitus is offline aparatusonitus  Croatia
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@Ian,

Do you have a VDMOS model for IRF710, thank you?
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Old 2nd April 2019, 06:56 AM   #213
UltimateX86 is online now UltimateX86  France
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Quote:
Originally Posted by IanHegglun View Post
Hi UltimateX86, See attached.
thank you very much Ian, thank you also for the Exicon that I use a lot right now
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Old 2nd April 2019, 11:42 PM   #214
IanHegglun is offline IanHegglun  Australia
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Default IRF710 VDMOS model, updated IRF610 IRF9610

Quote:
Originally Posted by aparatusonitus View Post
@Ian,
Do you have a VDMOS model for IRF710, thank you?
Hi All,

IRF710 below.
NB: My earlier IRF610/9610 model has been updated: Rd, Ron, Qg corrected.
Saturation region parameters were OK. The earlier models still work OK just better now when clipping. They are still not perfect but quite useable.

*VDMOS with subthreshold (c) Ian Hegglun Apr 2019
.model IRF610 VDMOS (Rg=5 Vto={4.30-6m*(0+temp-25)} Lambda=3m
+ Rs={35m*(1+3.5m*(0+temp-25))} Kp={0.5/(1+8.8m*(0+temp-25))}
+ Ksubthres={0.23*(1+4m*(0+temp-25))} Mtriode={0.35} Rd={1*(1+5m*(0+temp-25))}
+ Cgdmax=260p Cgdmin=10p a=0.35 Cgs=125p Cjo=300p Tnom=temp
+ m=0.75 VJ=5 IS=1n N=1.3 Rb=0.01 Vds=200 Ron=1.5 Qg=8nC mfg=IH201904 )
*
*VDMOS with subthreshold (c) Ian Hegglun Apr 2019
.model IRF9610_ VDMOS (pchan Rg=6 Vto={(-3.76+2.5m*(0+temp-25))} Lambda=4m
+ Rs={68m*(1+3m*(0+temp-25))} Tnom={temp} Kp={0.35/(1+3m*(0+temp-25))}
+ Ksubthres={0.2*(1+4m*(0+temp-25))} Mtriode={0.5} Rd={2*(1+9m*(0+temp-25))}
+ Cgdmax=120p Cgdmin=15p a=0.26 Cgs=113p Cjo=207p Tnom=temp
+ m=0.75 VJ=2.5 IS=1p N=1.5 Rb=0.02 Vds=-200 Ron=3 Qg=11nC mfg=IH201904 )
*
*VDMOS with subthreshold (c) Ian Hegglun Apr 2019
.model IRF710 VDMOS (Rg=5 Vto={4.40-6m*(0+temp-25)} Lambda=3m
+ Rs={35m*(1+3.5m*(0+temp-25))} Kp={0.5/(1+8.8m*(0+temp-25))}
+ Ksubthres={0.23*(1+4m*(0+temp-25))} Mtriode={0.2} Rd={3*(1+5m*(0+temp-25))}
+ Cgdmax=260p Cgdmin=10p a=0.35 Cgs=150p Cjo=300p Tnom=temp
+ m=0.75 VJ=5 IS=1n N=1.3 Rb=0.1 Vds=400 Ron=3.6 Qg=17nC mfg=IH201904 )

The attached jig is useful for plotting Id/Vgs and Id/Vds by only changing one command line (nice). Presently compares IRF710 to IRF610. You can compare one being fitted to another to see what's changing (nice). You can compare n- with a p- by editing the 'pchan' to 'nchan' and reversing the Vto sign (don't forget to undo these when done). Enable the .Temp 25 150 for temp stepping.

BTW with the jig you can see the IRF710 is almost the same as the IRF610 except for higher Rd and diode series Rb. Mtriode changes when Rd changes - you choose Mtriode using the Id vs Vds, to fit the ending Vds for the triode region.

BTW2 the "(0+temp-25)" You can add "50" in place of the "0" in all instances and you can set the junction temperature of this power MOSFET 50 deg C more than the ambient set by .Temp X (27C if not set).
I now prefer to set the junction temperature of my power MOSFET's by adding a Temp=X after the part name ('Value for M1'), eg, "IRF710 Temp=Tjp"
Then I add line .param Tjp=27
then add
.Step param Tjp List 27 77
This shows changes at start and after warmup with a Tj rise above ambient of 50C for the designated transistors.

BTW3 The above is useful for checking bias stability. You can do the same with bias diodes eg, "1N4148 Temp=Tjd" and define Tjd on a heatsink, eg,
.param Tjd=27+0.7*(Tjp-27)
where the "0.7" is the fractional drop from the power transistor junction to the heatsink sensing point, the ratio Rj-hs/Rj-a.

Cheers,
Attached Files
File Type: zip Compare-extractions-IRF610-IRF710.zip (2.3 KB, 21 views)
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Old 2nd April 2019, 11:50 PM   #215
keantoken is offline keantoken  United States
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Thanks for those models Ian.
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Old 3rd April 2019, 09:08 AM   #216
aparatusonitus is offline aparatusonitus  Croatia
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Excellent work Ian, very useful setup, thank you!
It would be very nice indeed if you could the same for IRFP9140 (for less then +/-40VDC supply) and IRFP340 (for less then +/-80VDC supply) as these are way more complementary devices than IRFP240 for IRFP9240...and yes, I do sound like a huntin dog chasing you...sorry!
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Old 3rd April 2019, 10:06 PM   #217
IanHegglun is offline IanHegglun  Australia
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Hi aparatusonitus,

I'll have a look next few days. BTW have you read my white paper explaining VDMOS parameter fitting? VDMOS - PAK2 devo
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Old 4th April 2019, 05:57 AM   #218
aparatusonitus is offline aparatusonitus  Croatia
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I'm embarrassed...I missed all the articles in your signature, unbelievable...the good thing is I have a lot to read, understand and implement, thank you!
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Old 4th April 2019, 08:07 AM   #219
IanHegglun is offline IanHegglun  Australia
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Hi aparatusonitus,

If you are interested in symmetry, did you see my recent Echo amp circuit?
Spice model for Russian KP903A JFET?
Quote:
I have written a paper explaining the options for making a practical 50W or 100W using this arrangement. It is here IansEchoAmp - Google Drive
I thought of it for LU1014D's. But now propose 5th generation trench MOSFET's. Most are aware generations after the IRF640 generation can't be used in linear mode direct off the +/-40-80V rails due to thermal hot spots (Spirito effect). But using them as Rush pairs with RET power transistors you get true symmetry and a wider better crossover region. Still just simulations.

Cheers,
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Old 4th April 2019, 09:26 AM   #220
aparatusonitus is offline aparatusonitus  Croatia
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Interesting ... but I would rather spend time and money on Sony/Yamaha/NEC V-fet (SIT) because I have a fair amount of each (I even have the "non-existent" and unobtainable Yamaha 2SJ27 but not a single one 2SK77
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