F5 power amplifier

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#8,803
chchyong89 said:
Hi everyone, Recently i tried to plug my headphone into F5, and notice there is zyyyyyyyyyyyyy~ sound from one of the channel while another channel no such problem. What is the problem that might causing this. perhaps not ground issue because i am using star ground symmetrically on both channel.

I tend to move around the signal cables around and notice that the noise will going louder when i move it near to the heat-sink. But take in consideration of the other channel's signal wires is lay on heatsink, which has no problem at all.

I tried to measure the DC offset, it's just around 4~5mv something.

Any other way to troubleshoot?
Click to expand...

Did you ground the heatsink?

_-_-bear
 
#8,805
chchyong89 said:
Hi everyone, Recently i tried to plug my headphone into F5, and notice there is zyyyyyyyyyyyyy~ sound from one of the channel while another channel no such problem. What is the problem that might causing this. perhaps not ground issue because i am using star ground symmetrically on both channel.
?
Click to expand...

Well, do your headphones have 3 wires? And where did you connect the wires to?
 
#8,812
I'm sorry, but I also don't understand how you get to that conclusion.

The first graph showed two Idss matched devices, so the bias current is the same if Vgs =0. But the characteristics are vastly different due to the different Yfs, and hence they cannot be considered as complementary IMHO.

The second graph showed two devices with different Idss. The one with degeneration has a deliberately chosen higher Idss so that they end up complementary after adding the 75 ohm source resistor. As such, you can operate them at any point and they are still complementary.

And incidentally, the JFETs in the F5 circuit do not operate at Idss, due to the 10 ohm resistor in parallel with the 50 ohm feedback resistor. At no signal, it is equivalent to a degeneration of ca. 8.3 ohm.

Perhaps you can explain your reasoning in a bit more detail.


Patrick
 
#8,813
Are you kidding me? Two words...DC bias...you choose a bias point (on your graphs it looks like the Idss matched jfets are complementary at Idss -even without the magic Rsource) and you make sure it doesn't vary...Cascoding, CCS, Voltage Regulation, Class A bias, sweet spot, etc...basically NP's list.

In every design there's always a compromise...the F5 needs some feedback.
 
#8,814
Blues said:
it looks like the Idss matched jfets are complementary at Idss
Click to expand...
the jFETs pass the same Id when the Idss has been selected or degenerated to be the same.
That is not complementary nor matched.
The slope of the Id vs Vgs curve must also match at the chosen operational Id or range of Id that you plan to use.
It's actual Id AND Slope that make the selected pair into a matched pair.
 
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