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UAC2 DAC + ADC with synchronized separate sampling
UAC2 DAC + ADC with synchronized separate sampling
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Old 10th February 2020, 12:21 PM   #1
phofman is online now phofman  Czech Republic
diyAudio Member
Join Date: Apr 2005
Location: Pilsen
Default UAC2 DAC + ADC with synchronized separate sampling

Latest inexpensive USB DACs with ESS chips have excellent params, up to 768/24. Getting better with every new DAC version. E.g. Khadas Toneboard for 99USD.

Parallel-output ADC with external clock - e.g. 24bit EVAL-AD7760 for 65USD EVAL-AD7760EDZ Analog Devices | Analog Devices EVAL-AD7760EDZ ADC Evaluation Board for AD7760 | 698-1407 | RS Components

The Khadas board has two crystals for each audio rates family(24.576MHz, 22.5792MHz), switched by the USB host, the selected clock signal is available at its external socket.

The AD7760 board has an SMB jack for external clock (buffered with NC7S08). Depending on its configured filter setup it could sample at 3.072MHz (24.576/2/4). That would allow running DAC at 768kHz and ADC at 4x that synchronously, being able to sample higher harmonics of a DUT fed with the DAC signal. Synchronous DAC/ADC clock is important as it allows precise FFT of the measurement signal.

A simple short-traced pinheader adapter board would connect the ADC board's pin header to RPi4 GPIOs header, digital levels should be compatible (2.5V ADC, 3.3V RPi). Optionally level shifting 3.3V DAC MCLK -> 5V ADC MCLK for optimal operation (as mentioned in the AD7760 datasheet, not required for the start).

Both boards have complete documentation available (schematics, PCB layout).

Measurement signal generator on linux host -> USB async at 768kHz/24bit -> Khadas board -> DUT -> AD7760 board -> 16bit parallel + control on RPi4 GPIOs read by kernel thread running on isolated CPU core -> USB UAC2 async gadget at 1536/24 or 3072/16 (for now, possible to support 3072/24 later) -> different USB port of the same linux USB host -> any software analyzer (fft - jaaa, scope).

Switching DAC/ADC samplerates would be synchronized, any combination supported by the HW would be available.

A different ADC could be used, requiring just a different communication channel in the special kernel thread on RPi (e.g. SPI, but the parallel bus has the highest throughput).

I cannot develop the analog circuits, but I am willing to take the RPi4 part. I am working on the async UAC2 gadget anyway. IMO it could be an interesting and potentially useful low-cost project.
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