LRCK
WCLK
BCLK
DATA
XTAL
= too many signals ?
Those are the signals for Sony CX23034 on a DAC board of a Teac CDP.
The XTAL is fed by a 16,9 MHz clock on board.
How can I connect to CS8412 ?
I guess:
SDATA --> DATA
FSYNC --> LRCK
SCK --> BCK
MCK --> XTAL and disconnect the crystal.
??? --> WCLK ???
WCLK
BCLK
DATA
XTAL
= too many signals ?
Those are the signals for Sony CX23034 on a DAC board of a Teac CDP.
The XTAL is fed by a 16,9 MHz clock on board.
How can I connect to CS8412 ?
I guess:
SDATA --> DATA
FSYNC --> LRCK
SCK --> BCK
MCK --> XTAL and disconnect the crystal.
??? --> WCLK ???
Dear Bernhard
Sounds like the signals you have identified are those
leaving an x times oversampling chip to connect to a DAC.
ie one step away from being a reformed analogue
waveform albiet with current to voltage conversion
which is usually performed by an op amp.
A CS8412 ( if you really have to use one ) rather typically
receives an SPDIF multiplex code originating close to the CD players processor. A CS8412's outputs are BCK LRCK and
DATA, these same codes are resident on the CD players
board. using flip flops on the transmission end and reception
end with a 75 ohm driver between its possible to
bypass SPDIF altogether.
It would be unusual to convert these final signals back
into SPDIF, in fact very difficult if not near impossible
Hope this helps Cheers / Chris
Sounds like the signals you have identified are those
leaving an x times oversampling chip to connect to a DAC.
ie one step away from being a reformed analogue
waveform albiet with current to voltage conversion
which is usually performed by an op amp.
A CS8412 ( if you really have to use one ) rather typically
receives an SPDIF multiplex code originating close to the CD players processor. A CS8412's outputs are BCK LRCK and
DATA, these same codes are resident on the CD players
board. using flip flops on the transmission end and reception
end with a 75 ohm driver between its possible to
bypass SPDIF altogether.
It would be unusual to convert these final signals back
into SPDIF, in fact very difficult if not near impossible
Hope this helps Cheers / Chris
Confusion...
I have a board from a CDP. Not the whole CDP.
It has an os chip CX23034 which originally gets its signals from a CX 23035 or so.
The input signals of the CX23034 are
LRCK
WCLK
BCLK
DATA
XTAL
Now I need to connect the CX23034 to the receiver to use that board as a DAC.
I can not bypass the CX23034 ( I would like to ) because I do not know what it outputs, and I do not know what are the required input signals of the next chip.
No datasheet of both of them.
I have a board from a CDP. Not the whole CDP.
It has an os chip CX23034 which originally gets its signals from a CX 23035 or so.
The input signals of the CX23034 are
LRCK
WCLK
BCLK
DATA
XTAL
Now I need to connect the CX23034 to the receiver to use that board as a DAC.
I can not bypass the CX23034 ( I would like to ) because I do not know what it outputs, and I do not know what are the required input signals of the next chip.
No datasheet of both of them.
Bernhard said:
XTi is 384Fs, BCLK is 48Fs, WCLK is 2Fs and LRCK is Fs and thats the easy bit.
MCLK from the CS8412 is always 256Fs and in master mode BCLK/SCK is always 64Fs. In order to interface the two, you would have to run the CS8412 in slave mode and derive all the clocks from the 384Fs clock driving the CX23034. Before the naysayers cry "dropout!!", the CS8412 has a two sample buffer in slave mode and if that is not enough, one can derive the 384Fs clock from a VCXO referenced to the code violations in the raw SPDIF stream.
BTW what dac is the CX23034 connected to?
rfbrw said:
So feed the 16 MHz clock from the DAC to the CS8412.
And connect data to data, SCK to BCK, and what is with WCLK and LRCK ?
The DAC is 2 x PCM53 with TEAC ZD ( noise added in a Teac chip and removed after PCM53 ) from a Tascam CDP, I think you remember those threads...
For testing I could try The Teac ZD700 or Denon DCD1500, both have CX23035 which could feed the CX23034.
All those different formats start to go on my nerves
And I smell the next trouble as I plan to built a toploader transport based on Philips CD960 with CDM1 and need BB format.
As so many voices shout SPDIF is crap
Bernhard said:
But the CS8412 has no use for a 384Fs clock. MCLK is fixed at 256Fs and is always an output.
Fine
SCK from the CS8412 is 64FS. The CX23034 expects 48Fs, though it just may support a burst clock but that won't make things any easier for you.
Ask Sony. I'm sure somewhere in its many divisions lies the answer.
The DAC is 2 x PCM53 with TEAC ZD ( noise added in a Teac chip and removed after PCM53 ) from a Tascam CDP, I think you remember those threads...
For testing I could try The Teac ZD700 or Denon DCD1500, both have CX23035 which could feed the CX23034.
All those different formats start to go on my nerves
And I smell the next trouble as I plan to built a toploader transport based on Philips CD960 with CDM1 and need BB format.
As so many voices shout SPDIF is crap
Have you considered settling on a design and seeing it through to the end?
There was a thread about modding TEAC VRDS25, this one also contains a distortion reduction chip and 4 x AD1862.
IMHO data is inverted and to both inverted and noninverted data digital noise is added.
After DAC inverted is subtracted from noninverted so noise cancels and signal adds.
Because always noise is present, there is never very low signal level and low level signal distortion is reduced.
IMHO data is inverted and to both inverted and noninverted data digital noise is added.
After DAC inverted is subtracted from noninverted so noise cancels and signal adds.
Because always noise is present, there is never very low signal level and low level signal distortion is reduced.
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