Layout would be critical, having the output GND go through a small resistor instead of a contiguous ground plane isn't going to do the signal integrity a lot of good, all the signals would have to cross a split in the ground plane....
Marce, I think you are being picky. The ground routing is the least of the problems here.
The circuit is really a wonderful example of cargo cult engineering. All that's missing is galvanic isolation and series resistors on the I2S outputs.
The circuit is really a wonderful example of cargo cult engineering. All that's missing is galvanic isolation and series resistors on the I2S outputs.
cargo cult programmer may apply when an unskilled or novice computer programmer (or one inexperienced with the problem at hand) copies some program code from one place to another with little or no understanding of how it works or whether it is required in its new position.
Can you give me some pointers ?
Can you give me some pointers ?
😀 I was being gentle, my first though was is it necessary..... my second thought was probably not.
I always tend to start with the bus specification;
https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
I would also look for the numerous application notes out there...
I would use the term cargo cult engineering more to refer to a solution without a problem. The I2S bus is designed for use on a single board really, between a couple of ICs over a moderate distance... I know it is used of-board but this is not its intended use and I think this may create more problems that it would ever fix.
I always tend to start with the bus specification;
https://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
I would also look for the numerous application notes out there...
I would use the term cargo cult engineering more to refer to a solution without a problem. The I2S bus is designed for use on a single board really, between a couple of ICs over a moderate distance... I know it is used of-board but this is not its intended use and I think this may create more problems that it would ever fix.
Very good. If your circuit is not just a cut and paste from others you can justify your choices.
Why does I2S, in general, benefit from reclocking?
Why use 74AUP? It is intended for battery powered devices with small, multi-layered PCBs with impedance controlled traces. Its output is very sensitive to capacitance and cannot drive long signal lines.
Why use 220 or 440 ohm series resistors on some signals? Terminating resistors are supposed to match the impedance of the output gate and the PCB trace. What's the output impedance of 74AUP and what is the impendence of the trace, connector, and wire connected to it?
Why use async reclocking. Unless the incoming signal is synchronized with the relocking latch you are guaranteed increased jitter equal to the period of the reclock oscillator.
Why is it proper to reclock DAC signals, which are multiples of 44.1KHz and 48KHz, with 100MHz?
There's a lot more, such as your voltage regulator and oscillator circuits, but why bother.
>>I2S input clock having Jitter( because of PLL ,wrong Xtal, not bit perfect )<<
Reclocking will not fix any of that. In fact, if the I2S input is good your circuit will corrupt it.
>>DAC device to reclocker circuit will be within 1 inch distance .<<
Then what are the connectors for?
>>If required resistors will be used for matching Impedance .<<
OK, but whatever the value, they are in the wrong place.
>>We have modified circuit for Synchronous Reclocking and removed the 100Mhz . Maximum sampling rate is 192Khz<<
Your circuit is NOT synchronous.
Reclocking will not fix any of that. In fact, if the I2S input is good your circuit will corrupt it.
>>DAC device to reclocker circuit will be within 1 inch distance .<<
Then what are the connectors for?
>>If required resistors will be used for matching Impedance .<<
OK, but whatever the value, they are in the wrong place.
>>We have modified circuit for Synchronous Reclocking and removed the 100Mhz . Maximum sampling rate is 192Khz<<
Your circuit is NOT synchronous.
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