I'm in the decision whether or not to divide the VCXO reclock signal by 2.
If I reclock the DAC digital signals with a lower frequency clock, (by using an "ideal" N divider) from theory the absolute jitter will be the same but phase noise is better (by 6dB per division).
So, in principle, is it better to reclock SCK, DATA and FSYNC digital signal with a "f/2" clock instead of "f" ? (i.e. 5.6MHz, instead of 11.2MHz) ?
Measurements of jitter reduction are exacly the same in the two cases (Jitter J-test), but sound appears just slightly better with the lower re-clock.
Any idea? Thanks!
http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt
If I reclock the DAC digital signals with a lower frequency clock, (by using an "ideal" N divider) from theory the absolute jitter will be the same but phase noise is better (by 6dB per division).
So, in principle, is it better to reclock SCK, DATA and FSYNC digital signal with a "f/2" clock instead of "f" ? (i.e. 5.6MHz, instead of 11.2MHz) ?
Measurements of jitter reduction are exacly the same in the two cases (Jitter J-test), but sound appears just slightly better with the lower re-clock.
Any idea? Thanks!
http://www.delroy.com/PLL_dir/FAQ/FAQ7.txt
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I don't believe dividing off the clock will do any good in this case.
The phase noise gets lower in an ideal frequency divider because you have the same amount of time error (jitter) on a longer period time. The phase error is their ratio multiplied by 2 pi radians, so the phase error gets smaller. But in a reclocker, the input frequencies are the output frequencies, no matter whether you divide the clock.
By the way, the 6 dB per division by two rule only applies to close-in phase noise unless you make a very exotic frequency divider, see https://www.diyaudio.com/forums/digital-line-level/273474-dac-dac-195.html#post5778250
The phase noise gets lower in an ideal frequency divider because you have the same amount of time error (jitter) on a longer period time. The phase error is their ratio multiplied by 2 pi radians, so the phase error gets smaller. But in a reclocker, the input frequencies are the output frequencies, no matter whether you divide the clock.
By the way, the 6 dB per division by two rule only applies to close-in phase noise unless you make a very exotic frequency divider, see https://www.diyaudio.com/forums/digital-line-level/273474-dac-dac-195.html#post5778250
Hi Marcel, thank you for the reply, I know you are very smart on PLL!
In fact jitter measurements this time tell nothing, as they are the same in both cases.
My doubt comes from that, since I'm reclocking tre different signals (at 2.8MHz, at 44.1KHz, and at the streaming data) with a unique 11.28MHz clock, this frequency could be too fast for at least the 44.1KHz signal.
So I'm thinking that reckloking at 11.28/2 = 5.6MHz the three I2S signals, is much closer to those frequency, and with the same amount of absolute jitter, hence better.
I cannot divide further as the highest frequency to reclock is 2.8MHz, so I need at least twice of it to clock the flip flop.
But 11.28Mhz reclocker is 256x higher than 44.1Khz, and 4x higher than 2.8Mhz. Is it too much fast for its duty?
I assume that you reclock your I2S signals with a clean clock that's synchronized to the incoming bit clock, presumably using the PLL that you wrote about in another thread.
As long as the flip-flops can handle it and as long as you can meet set-up and hold time requirements, there is nothing wrong with using a high clock rate. If the input signal would have such large jitter that the edges can shift by almost a complete clock period of the 11.2896 MHz or more, then you would have to use a lower clock rate to ensure that set-up and hold times are met - but you would have noticed it if there were a set-up and hold time issue.
As long as the flip-flops can handle it and as long as you can meet set-up and hold time requirements, there is nothing wrong with using a high clock rate. If the input signal would have such large jitter that the edges can shift by almost a complete clock period of the 11.2896 MHz or more, then you would have to use a lower clock rate to ensure that set-up and hold times are met - but you would have noticed it if there were a set-up and hold time issue.
That is correct Marcel. By recklocking the three I2S signals via filp flops with 11.2MHz or 5.6MHz clean clock works whitout problems.
Now I'm wondering why by using a 11.2 Mhz or 5.6 MHz to reclock, jitter measurements are exacly the same, THD% are exactly the same at 0dB ,-60dB and -80dB, but they sound different!
And, now, I like both way!
With 11.2MHz sound is more open and midforward, the bass is smooth and full; with 5.6Mhz (half recklock frequency) sound is more detailed, clean and bass are tight and soundstage more focused.
It seems theory doesn't help here this time. I'm probably going to make a selector on the panel to change the reclock frequency on the fly...
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If you divide with a flip flop, you can't change the absolute amount of jitter. This is because the flip flop is directly clocked by the main clock.
You can use a pll to divide the clock, this can improve of worsen the amount of jitter depending on the design of the pll.
On a side note, what protocol did you use to determine the sound quality of the different clock rates?
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Correct, I'm using a PLL and it is true that not always it will improve jitter if not correctly implemented.
I know that I should do an AB random select comparative blind test to be correct and scientific, but I cannot implement it now. Usually I cover my machines and ask my son to random switch between A and B. But here it is impossible because I would recognise the two frequencies because they have different but specific PLL locking time and noise signature.
I will take some few extra days to decide. The DAC must be ready by this month.
In principle SCK should be the most important to reclock.
Are you saying that it is "enough" to reclock just SCK, or that could be even worse to reclock also DATA and FSYNC?
Frankly, I didn't test to reclock just SCK...
When you report that the jitter measurments are the same, is that measurement a single figure representing the total jitter? If it is, then the next question would be; are the jitter spectrum plots identical? If they are not, the difference in sound you hear is probably due to differences in the character of the two jitter spectrums.
I was wrong!
The most important I2S to reclock is the LE (latch enable) signal or FSYNC!
Bit clock or SCK is just for shift register inside DAC. The most critical point is the where the conversion starts and that's triggered by LE signal in the PCM56.
I'm using now 11.xx MHz PLL reclock for both Clock SCK and Data, and 2.8MHz (one fourth) for FSYNC latch enable.
Jitter improved!
Also 11.xx MHz PLL reclock for both Clock SCK and Data, and 5.6MHz (one half) for FSYNC latch enable, is ok, I would say equivalent.
Both the ways are better than reclocking the three I2S signals with the same PLL frequency at 11MHz.
Strange: I cannot reclock FSYNC (44.1KHz) lower than 2.8MHz (tested 1.4MHz), as it doesn't work......
I'm using CS8412+PCM56 in Mode 5 (Out, L/R, 16 Bits LSBJ). Sorry I mention "I2S", but in reality Mode5 is not I2S compatible.
Anyway in CS8412 we have three “legs” SCK, FSYNC, SDATA.
The PCM56 is a mono DAC and has three “legs”: BCK, LE, DATA; left and right DATA is expected to be in parallel with a falling edge at LE triggering conversion. A low LE tells the DAC the DATA is meant for it.
From the datasheet the data is loaded into the PCM56 register according to the BCK (SCK) cycles. For updating the DAC (Latch), we must produce a differential from a high level to a low signal LE (FSYNC) “after” downloading the DATA of the left and right channels.
I found many different circuitry solutions to separate the left and right DAC streaming data into two PCM56 chips.
The best should be a "stopped clock" circuit by interrupting the clock frequency of loading data into one DAC register. This has no delay between the channels but requires more logics which add jitter.
I'm using a simple inverting configuration of the FSYNC/LE signal as the flip flop here has a double function: first to reclock SCK, FSYNC, SDATA and second to invert the FSYNC signal nearly synchronously between the two channels: the difference in propagation delay between Q and inverted \Q outputs in the same chip is less than 1ns using a 74F74 !
So in my case the FSYNC timing is the most important to reclock as it is the one that "updates" the DAC chip via LE "latch enable" pin, “after” having downloaded the DATA of the left and right channels into the DAC.
But I still don't know why I cannot reclock (as it doesn't work) FSYNC (LE) signal less than 2.8 MHz, as the frequency of FSYNC is much lower...
Sorry for the misunderstanding, you are absolutely right. I built a similar reclocker but for a different DAC chip that is TDA1540P. The CD player has dual mono DAC L/R, like yours. I reclocked the LE signal with a SN74S74 dual D-flip-flop to the master clock 4.2336 MHz. For avoiding metastability the two flip-flops are connected in cascade: input LE goes to D1, Q1 goes to D2, output Q2 (=reclocked LE) goes to the DAC, CK1 and CK2 tied together and receives the master clock. Try it this way.
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