In an old ESS app note here
http://www.esstech.com/files/4514/4095/4306/Application_Note_Component_Selection_and_PCB_Layout.pdf
It describes using an inverted MCLK in synchornous mode.
What was exactly is an inverted MCLK from a practical standpoint?
I've been struggling to figure this out all day.
Simply inverting the output of an XO and sending into the dac doesn't do anything.
I thought maybe what it means is to invert all of the data lines so it is effectively 180 degrees out of phase with the MCLK but I'm not so sure.
Could someone inform me of how this "inverted MCLK" is implemented?
http://www.esstech.com/files/4514/4095/4306/Application_Note_Component_Selection_and_PCB_Layout.pdf
It describes using an inverted MCLK in synchornous mode.
What was exactly is an inverted MCLK from a practical standpoint?
I've been struggling to figure this out all day.
Simply inverting the output of an XO and sending into the dac doesn't do anything.
I thought maybe what it means is to invert all of the data lines so it is effectively 180 degrees out of phase with the MCLK but I'm not so sure.
Could someone inform me of how this "inverted MCLK" is implemented?
Suggest you try putting dac in master mode and see when (in what relative phase) it exports BCLK and LRCK relative to MCLK. That would probably give a clue of what it thinks the PCM timing should be relative to MCLK, they you could see if inverting MCLK might have any benefit for reproducing that timing in sync mode.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.