Hi all,
I'm currently undertaking this project featuring an SPDIF input, FPGA DSP and 6 analogue outputs with PGA2311 volume control. Some more specs off the top of my head:
- Three stereo FIR filters with 2048 taps. 32bit coefficients and 24bit outputs. Six differential audio channels in total at 48kHz sample rate.
- WM8804 SPDIF input IC.
- Three PCM1754 DACs at 24bits.
- Three PGA2311 volume control ICs controlled from the FPGA and a rotary encoder with 7 segment display.
- 0.0015% THD best case.
- USB update.
- FIR coefficients are generated by rePhase and converted and sent to the device via a Python script. Coefficients can be updated on-the-fly.
The reason I'm posting this is because I think I'm going to make the PCBs availible to buy and wondered if anyone would be interested in them. The schematics, software and HDL will be available for free so you can make your own.
I haven't got too much information here as I'm doing this at work on my lunch break. The project isn't 100% finished. The FIRs are implemented and I've been listening to the system, I just need to finish off the remote update feature. This is a competitor to the miniDSP products, it's essentially a miniDSP 2x4 with more channels and better performance (hugely better noise!). I designed the system for active speaker projects. I'm going to be designing a 6 channel 1800W class D amplifier, too.
Thanks
Boscoe
I'm currently undertaking this project featuring an SPDIF input, FPGA DSP and 6 analogue outputs with PGA2311 volume control. Some more specs off the top of my head:
- Three stereo FIR filters with 2048 taps. 32bit coefficients and 24bit outputs. Six differential audio channels in total at 48kHz sample rate.
- WM8804 SPDIF input IC.
- Three PCM1754 DACs at 24bits.
- Three PGA2311 volume control ICs controlled from the FPGA and a rotary encoder with 7 segment display.
- 0.0015% THD best case.
- USB update.
- FIR coefficients are generated by rePhase and converted and sent to the device via a Python script. Coefficients can be updated on-the-fly.
The reason I'm posting this is because I think I'm going to make the PCBs availible to buy and wondered if anyone would be interested in them. The schematics, software and HDL will be available for free so you can make your own.
I haven't got too much information here as I'm doing this at work on my lunch break. The project isn't 100% finished. The FIRs are implemented and I've been listening to the system, I just need to finish off the remote update feature. This is a competitor to the miniDSP products, it's essentially a miniDSP 2x4 with more channels and better performance (hugely better noise!). I designed the system for active speaker projects. I'm going to be designing a 6 channel 1800W class D amplifier, too.
Thanks
Boscoe
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Hi Boscoe,
this is an awesome project. good job. may be you havent received the proper audience, I m sure there are tons of people looking for a better miniDSP
in my view providing the PCB without the assembly might not help diyer regarding the number of ICs on the board. but offering the complete board for 150 bucks would be of many interrest.
I m impressed with FPGA possibilities... you managed to put 12k taps in total ???!
one of the minidsp weakness is also the jitter (master clock) may I ask how you solved this ? I guess you are using the MCLCKOUT of the WM880x to drive the DACs , even if there is no spdif signal , right ? not bad this was used in some Arcam products
a better solution you might investigate for a another release is to drive the DACs with a low phase noise crystal, implement the SPDif receiver within the FPGA and implement an ASRC for taking care of the 2 clock domains inherent with this approach.
I m working on a same kind of projet with AKM449x and ICE40UP5K so I will follow this thread with interrest
this is an awesome project. good job. may be you havent received the proper audience, I m sure there are tons of people looking for a better miniDSP
in my view providing the PCB without the assembly might not help diyer regarding the number of ICs on the board. but offering the complete board for 150 bucks would be of many interrest.
I m impressed with FPGA possibilities... you managed to put 12k taps in total ???!
one of the minidsp weakness is also the jitter (master clock) may I ask how you solved this ? I guess you are using the MCLCKOUT of the WM880x to drive the DACs , even if there is no spdif signal , right ? not bad this was used in some Arcam products
a better solution you might investigate for a another release is to drive the DACs with a low phase noise crystal, implement the SPDif receiver within the FPGA and implement an ASRC for taking care of the 2 clock domains inherent with this approach.
I m working on a same kind of projet with AKM449x and ICE40UP5K so I will follow this thread with interrest
Last edited:
Hi Boscoe,
this is an awesome project. good job. may be you havent received the proper audience, I m sure there are tons of people looking for a better miniDSP
in my view providing the PCB without the assembly might not help diyer regarding the number of ICs on the board. but offering the complete board for 150 bucks would be of many interrest.
I m impressed with FPGA possibilities... you managed to put 12k taps in total ???!
one of the minidsp weakness is also the jitter (master clock) may I ask how you solved this ? I guess you are using the MCLCKOUT of the WM880x to drive the DACs , even if there is no spdif signal , right ? not bad this was used in some Arcam products
a better solution you might investigate for a another release is to drive the DACs with a low phase noise crystal, implement the SPDif receiver within the FPGA and implement an ASRC for taking care of the 2 clock domains inherent with this approach.
I m working on a same kind of projet with AKM449x and ICE40UP5K so I will follow this thread with interrest
Thanks Maxidcx. I was thinking that!
Hmmm true however I'm not sure it would be possible to sell it for that price, all the components aren't too far off that and then there's assembly cost.
Yes, FPGAs are good for this sort of thing due to their parallel nature. Need another FIR? Just add it in, takes not more time to process. The limiting factor with FPGAs is the size of their internal memory/simplicity. You could use some DDR3 and have huge FIRs but that would make this into a very different project. Currently i have 6k taps in this design as the left and right share the same coefficients, but yes I am processing 12k taps worth of data between 6 channels. I'm using a low-end cheap FPGA, bigger ones could have awesome possibilities which are unnecessary in my option. I'm only using about 8% of the FPGA fabric in this design, all the usage is in the memory.
I'm using the clock from the WM8804 for the input side of the data flow (clocking into the FIRs) then running the clock through a PLL which is connected to the I2S clock generation to clock the data out of a small FIFO (32 samples) into the DACs. This seems to be fine with very good THD and noise. I don't have a test for IMD but I can't see any evidence for it by eye on a spectrum analyser. In all honesty, jitter ins't such a big deal - I think there's a lot of hype there from audio companies selling people things.
Sure, well soon I will make the HDL available. I have written it for the M9K memory blocks in the Cyclone IV however it wouldn't be difficult to modify it or even write them from scratch - they are simple.
This is a very interesting project! I don't know about Altera because I'm a Xilinx person. But QFP is not used for a high-density chip. The FPGA may be similar to xc6slx9 which can also have four 2048 taps FIR(36bit by 36bit at 96k sample rate) at least. I'm sure 150 bucks is possible for Chinese manufactures but impossible for the Japanese one.
As to jitter, I agree with you. As long as your target is not above 110dB THD+N, you don't need to take care much about jitter from my experience. DAC chips usually don't have such high performance and not necessary for normal audio application where you listen to music, not intend to achieve the highest THD+N.
As to jitter, I agree with you. As long as your target is not above 110dB THD+N, you don't need to take care much about jitter from my experience. DAC chips usually don't have such high performance and not necessary for normal audio application where you listen to music, not intend to achieve the highest THD+N.
Things have come on a long way over the years with FPGA's.
In 1984 we worked on a programmable chip for doing Teletext.
The engineer who did it got the data the wrong way around, so I had to flip it in software before I could use it.
In the 1990's I worked on a custom FPGA for a Ford ECU.
In those days we used schematic entry and not VHDL.
In 1984 we worked on a programmable chip for doing Teletext.
The engineer who did it got the data the wrong way around, so I had to flip it in software before I could use it.
In the 1990's I worked on a custom FPGA for a Ford ECU.
In those days we used schematic entry and not VHDL.
My first experience with FPGA was ORCA which was developed by Bell Labs in early 90's. I used to use GA which was not field programmable in the 80's. GA was terribly inconvenient because it needed careful software simulation before manufacturing. It forced you to remanufacture even if there was one fault. Field programmable changed the world. The basic architecture of FPGA is still not changed from Bell Labs. They were great.
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