The PCM5102A chip (which I am working with) has two options for the clock - either by applying a signal to the SCK pin, or by using "PLL Mode". The datasheet states:
"The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high
frequency electromagnetic interference. The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference."
My (unfinished) schematic is below, and the PCM5102A is currently connected to the DIR9001 using all 4 wires (with the DIR9001 providing the clock). Is there an advantage to using the "PLL Mode", or will it be better to just stick with my original plan?
"The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high
frequency electromagnetic interference. The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference."
My (unfinished) schematic is below, and the PCM5102A is currently connected to the DIR9001 using all 4 wires (with the DIR9001 providing the clock). Is there an advantage to using the "PLL Mode", or will it be better to just stick with my original plan?
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