Hi All,
See AudioBox, an FPGA experiment - an FPGA experiment that got way out of hand...
Apologies to the moderator, I posted in the wrong forum last time, hopefully this is a little more appropriate.
Regards,
Mark
See AudioBox, an FPGA experiment - an FPGA experiment that got way out of hand...
Apologies to the moderator, I posted in the wrong forum last time, hopefully this is a little more appropriate.
Regards,
Mark
That's interesting design, I've been planning something similar for using as active crossover - would you think it could be built on DE0-Nano? I was thinking to actually use a ADC (or SPDIF digital receiver with I2S out) and four DACs (24-bit/96 kHz) as I/O.
There is btw. a book "Embedded SoPC Design with Nios II Processor and Verilog Examples" (see Companion Web site for FPGA Prototyping by Verilog Examples ) that's quite a like similar system like AudioBox. I haven't got that (quite a bit expensive) but looked at the examples to get the idea. Still don't exactly know how the I/O part with FIFO's could be combined with DSP code, should there be similar FIFO's for DSP blocks so that the channels could be routed to different DSP functions via C-code running in NIOS?
There is btw. a book "Embedded SoPC Design with Nios II Processor and Verilog Examples" (see Companion Web site for FPGA Prototyping by Verilog Examples ) that's quite a like similar system like AudioBox. I haven't got that (quite a bit expensive) but looked at the examples to get the idea. Still don't exactly know how the I/O part with FIFO's could be combined with DSP code, should there be similar FIFO's for DSP blocks so that the channels could be routed to different DSP functions via C-code running in NIOS?
Hi mhelin,
There is a good chance you could get what you want done as you describe. Break the design into blocks: I2S in, I2S out, Convolution Engine, Shared memory between CE and NIOS II, Coefficient Generation (NIOS II), User Interface (NIOS II), glue to hold it all together ... or something similar.
Huge amount of work, masses to learn. Modular and scalable, so you can build and test bits independently.
Maybe get a small stereo DAC and ADC board, attach DE0-nano, get basic I/O working. Get soundcard audio test setup that allows freq sweep, add filter to FPGA, then examine response using freq sweeper of ADC + filter + DAC.
If you want to go with the eas(ier) way, go with ADAU1442. I prefer the FPGA.
Also look at ISBN 978-0240825151 "Designing Audio Effect Plug-Ins in C++: With Digital Audio Signal Processing Theory".
Regards,
Mark
There is a good chance you could get what you want done as you describe. Break the design into blocks: I2S in, I2S out, Convolution Engine, Shared memory between CE and NIOS II, Coefficient Generation (NIOS II), User Interface (NIOS II), glue to hold it all together ... or something similar.
Huge amount of work, masses to learn. Modular and scalable, so you can build and test bits independently.
Maybe get a small stereo DAC and ADC board, attach DE0-nano, get basic I/O working. Get soundcard audio test setup that allows freq sweep, add filter to FPGA, then examine response using freq sweeper of ADC + filter + DAC.
If you want to go with the eas(ier) way, go with ADAU1442. I prefer the FPGA.
Also look at ISBN 978-0240825151 "Designing Audio Effect Plug-Ins in C++: With Digital Audio Signal Processing Theory".
Regards,
Mark
Yes, lot's of work because I'm just learner 
I've studied your I2S code and found already some bugs there - actually just typos. The begin was after marker reset (
) when I think it was supposed to be before that.
I think I'll order the DE0-NANO first. I've already got a Cyclone II board from ebay and blinked the leds. Then fpga4fun.com is excellent site for learning verilog. I've done DSP in C++ so that's no problem. It's more like transferring the DSP to verilog. I think most people agree that for an example IIR filters on FPGA are out of question, so I might indeed use convolution and FIR filters. You can make minimum phase ones as well so there is no extra latency involved.
The basic flow will always be the same: I2S in -> 2xdemux (1:4) -> 8x convolver engines -> 4xI2S out, so the switching is not needed at all, and the delays can be controlled also in the convolution block by adding enough zeroes in the beginning of coefficients (=shift right the data). Also the coefficients can be loaded from PC, or better yet from iPad or Android pad. They both support USB and maybe MIDI class devices as well(at least iPad does that). Just have to learn program IOS (Objective C I guess, or plain Java). Android pads are cheap (starting from $50 or so).
I've studied your I2S code and found already some bugs there - actually just typos. The begin was after marker reset (
Code:
marker <= 0;I think I'll order the DE0-NANO first. I've already got a Cyclone II board from ebay and blinked the leds. Then fpga4fun.com is excellent site for learning verilog. I've done DSP in C++ so that's no problem. It's more like transferring the DSP to verilog. I think most people agree that for an example IIR filters on FPGA are out of question, so I might indeed use convolution and FIR filters. You can make minimum phase ones as well so there is no extra latency involved.
The basic flow will always be the same: I2S in -> 2xdemux (1:4) -> 8x convolver engines -> 4xI2S out, so the switching is not needed at all, and the delays can be controlled also in the convolution block by adding enough zeroes in the beginning of coefficients (=shift right the data). Also the coefficients can be loaded from PC, or better yet from iPad or Android pad. They both support USB and maybe MIDI class devices as well(at least iPad does that). Just have to learn program IOS (Objective C I guess, or plain Java). Android pads are cheap (starting from $50 or so).
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Ohh err, yes, found the error. As written it is the only clause taken by else, and the blank begin/end pair are blank, so are ignored. Well done.
The DE0-nano has on-board programmer and the terASIC documentation is well worth going through - lots of basic, and essential things about Quartus and NIOS II as well as programming the on-board boot FLASH. Anyway, for US$85 you can't go wrong.
Not sure why you are concerned about an IIR filter in FPGA - it all comes down to architecture - and you have a 50MHz clock with ~48kHz audio, so plenty of cycles to do stuff. Having tinkered with FPGA for a year or so, if you can't do something it may mean that you just need to spend more time thinking about the problem.
Took me 2 weeks to get PCM -> dB conversion running at 1.3M conversions per sec. Lots of paper, spreadsheets and hair pulling, but got there eventually.
My only concern about using FIR filters is available memory space - you only have 600k bits available unless you use the 32M SDRAM and that is fiddly, and you only have one 'instance' of it.
Keep going, it sounds like you are heading in the right direction.
-mark
PS how do insert code snips into this thingy ??
The DE0-nano has on-board programmer and the terASIC documentation is well worth going through - lots of basic, and essential things about Quartus and NIOS II as well as programming the on-board boot FLASH. Anyway, for US$85 you can't go wrong.
Not sure why you are concerned about an IIR filter in FPGA - it all comes down to architecture - and you have a 50MHz clock with ~48kHz audio, so plenty of cycles to do stuff. Having tinkered with FPGA for a year or so, if you can't do something it may mean that you just need to spend more time thinking about the problem.
Took me 2 weeks to get PCM -> dB conversion running at 1.3M conversions per sec. Lots of paper, spreadsheets and hair pulling, but got there eventually.
My only concern about using FIR filters is available memory space - you only have 600k bits available unless you use the 32M SDRAM and that is fiddly, and you only have one 'instance' of it.
Keep going, it sounds like you are heading in the right direction.
-mark
PS how do insert code snips into this thingy ??
Just left order to Mouser, got DE0-NANO free of delivery charges for total of 93 euros including VAT (75 eur without).
Found good tutorial for setting up NIOS II with SDRAM etc. here:
https://sites.google.com/site/fpgaandco/
Found good tutorial for setting up NIOS II with SDRAM etc. here:
https://sites.google.com/site/fpgaandco/
Thanks.
Looks like a good tutorial. There is also a link to the DE0-nano documentation.
Just putting together some I/O cards for the DE0-nano (any suggestions for an abbreviation ?).
Digital JP1 side will have USB serial, USB parallel, Ethernet PHY, uSD card, bluetooth, buttons and LEDs.
Video JP2 board will have VGA, dual CVBS, YC, and 2 x 8MHz low pass filters.
RF JP2 board will have dual over-sampled DAC, I-Q up-converter and 100-2400MHz PLL, MMIC and SMA out (may be other stuff, still thinking about this one).
also see DigiLite-ZL, an Experimental DVB-S modulator and DigiLite-ZL and FPGA, an Experimental DVB-S modulator, continued...
... all getting rather OT for this group
Anyway, most interested to see how you get on. My email is at bottom of those links if you think I can help.
Looks like a good tutorial. There is also a link to the DE0-nano documentation.
Just putting together some I/O cards for the DE0-nano (any suggestions for an abbreviation ?).
Digital JP1 side will have USB serial, USB parallel, Ethernet PHY, uSD card, bluetooth, buttons and LEDs.
Video JP2 board will have VGA, dual CVBS, YC, and 2 x 8MHz low pass filters.
RF JP2 board will have dual over-sampled DAC, I-Q up-converter and 100-2400MHz PLL, MMIC and SMA out (may be other stuff, still thinking about this one).
also see DigiLite-ZL, an Experimental DVB-S modulator and DigiLite-ZL and FPGA, an Experimental DVB-S modulator, continued...
... all getting rather OT for this group
Anyway, most interested to see how you get on. My email is at bottom of those links if you think I can help.
Digital TV station, that would be interesting project. Anyway, thanks for help, it may last a while before I get something to write about (haven't got too much time of my own these days as a father of a 2 years old son). Might start a new thread for discussions though, I see FGPA used on these forums only on some USB I2S DAC's, not much for DSP. You haven't though adding the EQ or other digital FX to your box in addition of the gain control?
Yes, slowly working on the EQ engine, but lots of other stuff is getting in the way at the moment. Need to do simulations of the IIR coeff generator, then get white noise processed and analysed on a PC with the generated coeffs etc. Don't see any issue building required real time EQ engine when I know what I am doing, but that will be some time away.
regards,
Mark
regards,
Mark
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