low jitter crystal oscillator IC beta tester needed.

yizhou · 25th April 2013, 11:03 PM

Hi,
I am Yi Zhou from Accusilicon. We are looking for beta testers for our new low phase noise clock IC, T1. I will send each tester 10pcs of T1 chip. Any one interested please PM me.

Thanks!

yizhou · 26th April 2013, 12:53 AM

T1's block diagram:

low jitter crystal oscillator IC beta tester needed.

Test setup:

T1 Chip in SOT23-6 packages

T1+22.5792MHz crystal (digikey part 478-6888-1-ND) in today's test

T1+24.576MHz crystal (digikey part 887-1677-1-ND) in today's test:

iancanada · 26th April 2013, 02:15 AM

Hi, I might be interested in.

Ian

Iloveswan · 27th April 2013, 05:28 AM

Looks Nice. Count me in!

twest820 · 28th April 2013, 06:13 AM

Worthy phase noise graphs; nice. I've no immediate need for one (not much point applying a 500fs clock to a 50ps PLL) but for audio applications the T1 looks to be potentially quite competitive with parts like the CDCE62002 and LMK04800. Let us know when the preliminary datasheet's updated with details of the VC pin's functions and other basic information. (I see the X8C's datasheet remains quite preliminary after 11 months and http://t1calc.accusilicon.com/ is a 403 at the moment so it seems one should be prepared for a bit of a wait. I suppose the programming protocol could be figured out from reading the T1 tool sources. That might be a bit excessive though, since populating a register table in the datasheet and such probably only requires a copy/paste from the design spec.)

Something which might be worth considering as a compete is a reference design which includes clock fanout. When integrating a T1 with certain codecs or ESS DACs copying the clock is unimportant, either due to the DAC's ASRC or the codec's inclusion of a clock output. But in the common case where DACs from vendors other than ESS are used it's routine to need a jitter insensitive fanout to the DSP, DSC, or microcontroller driving the DAC along with jitter sensitive fanout to multiple stereo DACs. DIY applications tend to emphasize biamping or triamping but this need occurs in higher end 5.1 and 7.1 implementations as well as in professional audio interfaces.

25th April 2013, 11:03 PM	#1
yizhou diyAudio Member Join Date: Apr 2013 Location: Santa Clara, USA	low jitter crystal oscillator IC beta tester needed. Hi, I am Yi Zhou from Accusilicon. We are looking for beta testers for our new low phase noise clock IC, T1. I will send each tester 10pcs of T1 chip. Any one interested please PM me. Thanks!

26th April 2013, 12:53 AM	#2
yizhou diyAudio Member Join Date: Apr 2013 Location: Santa Clara, USA	T1's block diagram: Test setup: T1 Chip in SOT23-6 packages T1+22.5792MHz crystal (digikey part 478-6888-1-ND) in today's test T1+24.576MHz crystal (digikey part 887-1677-1-ND) in today's test:

26th April 2013, 02:15 AM	#3
iancanada diyAudio Member Join Date: Dec 2009 Location: Toronto	Hi, I might be interested in. Ian __________________ gitHub: https://github.com/iancanada/DocumentDownload GB2020Q3: https://www.diyaudio.com/forums/grou...ml#post6413248 YouTube Channel: https://www.youtube.com/channel/UC75...iy-PHSJB-8PgPg

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27th April 2013, 05:28 AM	#4
Iloveswan diyAudio Member Join Date: Oct 2010 Location: San Jose	Looks Nice. Count me in!

28th April 2013, 06:13 AM	#5
twest820 diyAudio Member Join Date: Jun 2009	Worthy phase noise graphs; nice. I've no immediate need for one (not much point applying a 500fs clock to a 50ps PLL) but for audio applications the T1 looks to be potentially quite competitive with parts like the CDCE62002 and LMK04800. Let us know when the preliminary datasheet's updated with details of the VC pin's functions and other basic information. (I see the X8C's datasheet remains quite preliminary after 11 months and http://t1calc.accusilicon.com/ is a 403 at the moment so it seems one should be prepared for a bit of a wait. I suppose the programming protocol could be figured out from reading the T1 tool sources. That might be a bit excessive though, since populating a register table in the datasheet and such probably only requires a copy/paste from the design spec.) Something which might be worth considering as a compete is a reference design which includes clock fanout. When integrating a T1 with certain codecs or ESS DACs copying the clock is unimportant, either due to the DAC's ASRC or the codec's inclusion of a clock output. But in the common case where DACs from vendors other than ESS are used it's routine to need a jitter insensitive fanout to the DSP, DSC, or microcontroller driving the DAC along with jitter sensitive fanout to multiple stereo DACs. DIY applications tend to emphasize biamping or triamping but this need occurs in higher end 5.1 and 7.1 implementations as well as in professional audio interfaces.