Hello guys!
Lately, I've been working intensively on Class D amplifiers.
Now, I have developed the following circuit and wanted to know what you think about it.
For example, I am not sure if I designed the negative feedback correctly.
Unfortunately, I cannot simulate the entire amplifier because I have not found any Spice models for the LM5104 and Si8610BB. I am using LTSpice, Multisim and Tina TI.
Important: R21, R32 and R34 are 0R jumpers and are for test purposes only.
At the end, R21 and R34 remain empty.
Thank you for your answers!
Best regards
Simi
si1505do@gmail.com
DIY Electronic Projects
Lately, I've been working intensively on Class D amplifiers.
Now, I have developed the following circuit and wanted to know what you think about it.
For example, I am not sure if I designed the negative feedback correctly.
Unfortunately, I cannot simulate the entire amplifier because I have not found any Spice models for the LM5104 and Si8610BB. I am using LTSpice, Multisim and Tina TI.
Important: R21, R32 and R34 are 0R jumpers and are for test purposes only.
At the end, R21 and R34 remain empty.
Thank you for your answers!
Best regards
Simi
si1505do@gmail.com
DIY Electronic Projects
Last edited:
MOSFETs have 26nC gate charge, yet you use only 10nF bootstrap caps? 33nF would be more logical choice, only drooping 1V or so in action.
The 10k resistors between gate and source on the MOSFETs load down the bootstrap circuit enormously, presenting a very low 25us time-constant with the gate capacitance, perhaps increase these to 100k or lose them. The gate driver should have under-voltage protection and clamp the devices off anyway, but a high value resistor to drain the gate with powered off might be wise.
The datasheet for the LM5104 mentions adaptive timing, which sounds like a recipe for unwanted jitter in the timing - it will make switching points dependent on the current levels by waiting for plateau voltage to pass. Setting fixed timing, although requiring more deadtime for safety, may be less distorting in the time domain, in otherwords perhaps a more standard driver chip would be better for class D.
Note it has on-board bootstrap diode, you don't need D3.
Some people favorite extra schottky diodes to backup the MOSFET body diodes and reduce the errors due to diode drops during transients.
The 10k resistors between gate and source on the MOSFETs load down the bootstrap circuit enormously, presenting a very low 25us time-constant with the gate capacitance, perhaps increase these to 100k or lose them. The gate driver should have under-voltage protection and clamp the devices off anyway, but a high value resistor to drain the gate with powered off might be wise.
The datasheet for the LM5104 mentions adaptive timing, which sounds like a recipe for unwanted jitter in the timing - it will make switching points dependent on the current levels by waiting for plateau voltage to pass. Setting fixed timing, although requiring more deadtime for safety, may be less distorting in the time domain, in otherwords perhaps a more standard driver chip would be better for class D.
Note it has on-board bootstrap diode, you don't need D3.
Some people favorite extra schottky diodes to backup the MOSFET body diodes and reduce the errors due to diode drops during transients.
I've built this amplifier in a slightly different way (unsymmetric power supply) before and made the following discovery:
Class D Amp. / Knick im Ausgangssinus unter Last - Mikrocontroller.net
The thread is unfortunately in German, but you can simply translate it.
I want to get that "kink" in sinewave away.
Is this due to the feedback or the LM5104 or something else?
Class D Amp. / Knick im Ausgangssinus unter Last - Mikrocontroller.net
The thread is unfortunately in German, but you can simply translate it.
I want to get that "kink" in sinewave away.
Is this due to the feedback or the LM5104 or something else?
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