JFET buffer with J113

[rhythmsandy]

You will not see .003% without extensive tweaking, something that Spice
is not anticipating for you. That simulated figure is simply the difference
between the Spice model and reality.

Changing R6 alters the current gain, as do other resistors.....

😉

Hi Nelson,

At what idle current does J113 provides the lowest distortion level.

 

[Nelson Pass]

Depends on the part, the bias, the supply voltage and the load.

If you are simply looking for the lowest number then you adjust these to cancel the second harmonic.

Myself, I generally prefer a slight 2nd harmonic of negative phase.

 

[rhythmsandy]

thanking for your reply Nelson. Consider in CCS source case and Single ended Jfet buffer case with very little current into the load as much as 100micro amps max

 

[Nelson Pass]

I tell you what: give me three of the four an I will give you the third.

 

[woody]

Nelson, wonder if you could use a pair of the LD1014D jfets with 10 ohm source resistors for a low output impedience buffer ?