Jitter is something new from me. I'm not sure I really understand what it is, what I understood is that it's some noise on digital signals, like a irregularity in the clock signal period, or an inconstant phase for the signal.
But what causes this?
I've read here that reclocking (synchronous or asynchronous) can reduce the jitter, with a low jitter clock driving flip flops
but that's "only" glue logic and a clock! ICs are also made of locig, and recieve a clock signal.
Why can't decoders, digital filters, etc output a jitter free (or low jitter) signal themselves, directly on theyr outputs. Why the need for reclocking?
But what causes this?
I've read here that reclocking (synchronous or asynchronous) can reduce the jitter, with a low jitter clock driving flip flops
but that's "only" glue logic and a clock! ICs are also made of locig, and recieve a clock signal.
Why can't decoders, digital filters, etc output a jitter free (or low jitter) signal themselves, directly on theyr outputs. Why the need for reclocking?
Jitter is the result of analog noise in digital circuits
All of the noise mechanisms you've ever heard of can cause jitter.
1/f and burst noise caused by impurities and defects in gain devices can cause huge shifts in timing signals (milliseconds and even seconds in the case of nearly but not failed gates). If you watch a submicron transistor on an oscilloscope, you will see surprising amounts of noise including random pulse trains. If you look at enough transistors or at particularly contaminated types of transistors, you can find 10's of millivolts of pulse and 1/f noise. Anyway, the point I'm making here is that there is some probability that even ic's with good reputations for low noise can have high noise. The cleaner the ic fabrication process is (and the closer the device's single crystal-ness is to perfection) the lower the probability of having an ic that is disappointing. There are very few tests for noise in the ic industry. Essentially none of the devices you care about have been tested for excess noise because the test time would require on the order of 10 seconds to a few minutes.
The other source of noise that is due to "defective" human causes is ground noise, which is due to poor layout of grounding. Guido Tent's website has probably the best simple discussion of this I'm aware of. Better than the larger Analog Devices discussion of grounding.
All other kinds of noise are due to physics - shot noise, thermal noise, kt/C noise and so on. Some of these can be improved through design awareness but usually that isn't something you can deal with at the diy level, except by selecting ic's that have been designed and fabricated with low noise.
I realize this only addresses a small part of your question, but someone else more qualified can discuss the effect of noise on timing critical operations.
By the way, the PC Music Player thread is looking for jitter expertise. We want some data and methods to measure jitter for our upcoming projects so we can compare our results and set a target for the worlds' best music player
.
-Robert
All of the noise mechanisms you've ever heard of can cause jitter.
1/f and burst noise caused by impurities and defects in gain devices can cause huge shifts in timing signals (milliseconds and even seconds in the case of nearly but not failed gates). If you watch a submicron transistor on an oscilloscope, you will see surprising amounts of noise including random pulse trains. If you look at enough transistors or at particularly contaminated types of transistors, you can find 10's of millivolts of pulse and 1/f noise. Anyway, the point I'm making here is that there is some probability that even ic's with good reputations for low noise can have high noise. The cleaner the ic fabrication process is (and the closer the device's single crystal-ness is to perfection) the lower the probability of having an ic that is disappointing. There are very few tests for noise in the ic industry. Essentially none of the devices you care about have been tested for excess noise because the test time would require on the order of 10 seconds to a few minutes.
The other source of noise that is due to "defective" human causes is ground noise, which is due to poor layout of grounding. Guido Tent's website has probably the best simple discussion of this I'm aware of. Better than the larger Analog Devices discussion of grounding.
All other kinds of noise are due to physics - shot noise, thermal noise, kt/C noise and so on. Some of these can be improved through design awareness but usually that isn't something you can deal with at the diy level, except by selecting ic's that have been designed and fabricated with low noise.
I realize this only addresses a small part of your question, but someone else more qualified can discuss the effect of noise on timing critical operations.
By the way, the PC Music Player thread is looking for jitter expertise. We want some data and methods to measure jitter for our upcoming projects so we can compare our results and set a target for the worlds' best music player
.-Robert
I think jitter is if the puls width varies from pulse to pulse, the high priod is not the same as the following low period and again the following high period is different from both recent periods and so on.
Maybe I'm wrong and jitter critter is something totally different 😀
Maybe I'm wrong and jitter critter is something totally different 😀
Noise -> time-shift in pulse
That's right. The timing of pulse transition is offset by the noise mechanisms I mentioned. The dc regulator is a good example. You want pure dc but it's not pure, there is ripple and random noise at some level. Due to finite PSRR, digital transitions will be faster or slower and will be earlier or later as the dc suppy fluctuates. Apparently, microvolts of noise on the supply of a dac ic will produce audible results.
-Robert
That's right. The timing of pulse transition is offset by the noise mechanisms I mentioned. The dc regulator is a good example. You want pure dc but it's not pure, there is ripple and random noise at some level. Due to finite PSRR, digital transitions will be faster or slower and will be earlier or later as the dc suppy fluctuates. Apparently, microvolts of noise on the supply of a dac ic will produce audible results.
-Robert
OK, thank you for your explanations 😉
Now the unansweared question is why aren't digital ICs such as decoders or digital filters capable of delivering a jitter free signal themsalves?
Now the unansweared question is why aren't digital ICs such as decoders or digital filters capable of delivering a jitter free signal themsalves?
They are
They will to a large degree be low jitter if you provide pure power and excellent decoupling and jitter-free input signals.
-Robert
They will to a large degree be low jitter if you provide pure power and excellent decoupling and jitter-free input signals.
-Robert
Also note that jitter doesn't matter for purely digital circuitry
(unless the jitter is so bad that you get bit errors, but then
all bets are off anyway). The only place where clock jitter
matters in a CDP, for instance, is in the last digital synchronization
step, that is, in the DA converter. Jitter may also matter for
reading the disc, but there we are anyway reconstructing a
digital signal so it is more like the first case where you either
get bit errors or it works.
(unless the jitter is so bad that you get bit errors, but then
all bets are off anyway). The only place where clock jitter
matters in a CDP, for instance, is in the last digital synchronization
step, that is, in the DA converter. Jitter may also matter for
reading the disc, but there we are anyway reconstructing a
digital signal so it is more like the first case where you either
get bit errors or it works.
Why?????
Because there are lots of things going on.......all at once.......using one ground lead, and one supply lead.
Instead of separate wires for each function.
Jocko
Because there are lots of things going on.......all at once.......using one ground lead, and one supply lead.
Instead of separate wires for each function.
Jocko
Re: Why?????
So does it mean that reclocking all the 3 I2S lines in one IC package (for example, a 74HC174) is bad?
Jocko Homo said:
So does it mean that reclocking all the 3 I2S lines in one IC package (for example, a 74HC174) is bad?
Re: Re: Why?????
Reclocking has to be done in reference all the way back to the source of the data. In a CD system this means the transport mech. To do this the digital data is fed to a FIFO using the clock that rides on the data. The data is then clocked out of the FIFO using a new clock. But if the FIFO is filling at uneven rates (ie, one clock is faster than the other) the FIFO will overrun and data is lost. To solve this, you send your clock back to the transport. Everything now runs in lockstep and Jitter is virtually eliminated.
A similar thing can be done using a PLL. The frequency of the "new clock" is continually adjusted until it, on the average, equals the frequency of the incoming clock. As long as the FIFO is big enough, the "on the average" part doesn't matter.
Bricolo said:
Reclocking has to be done in reference all the way back to the source of the data. In a CD system this means the transport mech. To do this the digital data is fed to a FIFO using the clock that rides on the data. The data is then clocked out of the FIFO using a new clock. But if the FIFO is filling at uneven rates (ie, one clock is faster than the other) the FIFO will overrun and data is lost. To solve this, you send your clock back to the transport. Everything now runs in lockstep and Jitter is virtually eliminated.
A similar thing can be done using a PLL. The frequency of the "new clock" is continually adjusted until it, on the average, equals the frequency of the incoming clock. As long as the FIFO is big enough, the "on the average" part doesn't matter.
Jocko Homo said:
Would be it an interestin' challenge use the 74HC74(example) for just one FF and so ,3 separated chips (or four)for the I2S line each one with its own power supply?
Please let me know of single FF package.
Thanks for the link.
In the 74HC74 DUAL FF , if I decide to use JUST one flip flop in one chip , what have I to do with the second?
I mean , how to connect the remainig pins of RnegD , D , Clock , SnegD , Q and Qneg ? At ground ? Need suggestion as I didn't find it in the datasheet.
In the 74HC74 DUAL FF , if I decide to use JUST one flip flop in one chip , what have I to do with the second?
I mean , how to connect the remainig pins of RnegD , D , Clock , SnegD , Q and Qneg ? At ground ? Need suggestion as I didn't find it in the datasheet.
let the output floating
put the inputs at zero
the set and reset to zero, but since they are active low, put them at 1
put the inputs at zero
the set and reset to zero, but since they are active low, put them at 1
OK Bricolo, Thanks Again.
But I in the maentime have already build a reclocker with 4 74hc74 -in use only one flop flop/chip- ( 4 comes from the fact that the dac is balanced) powered by a battery for each chip/FF and now I can say ah... it CHANGES A LOT ... A LOT guys .
It is just another story from the sonic point of view ah... another story.
But I in the maentime have already build a reclocker with 4 74hc74 -in use only one flop flop/chip- ( 4 comes from the fact that the dac is balanced) powered by a battery for each chip/FF and now I can say ah... it CHANGES A LOT ... A LOT guys .
It is just another story from the sonic point of view ah... another story.
How is youd dac balanced?
Are you inverting one of the 3 I2S lines to send it to the 2nd dac? If yes, throw the inverter away and use the Q' output of the FF
Are you inverting one of the 3 I2S lines to send it to the 2nd dac? If yes, throw the inverter away and use the Q' output of the FF
stefanobilliani said:OK Bricolo, Thanks Again.
But I in the maentime have already build a reclocker with 4 74hc74 -in use only one flop flop/chip- ( 4 comes from the fact that the dac is balanced) powered by a battery for each chip/FF and now I can say ah... it CHANGES A LOT ... A LOT guys .
It is just another story from the sonic point of view ah... another story.
Hi,
schematic ?
Bricolo said:
Not exactly. I have 4 XOR gates close to the saa7310 in the CD player and while 1 of that inverts the DATA, all thogether acts as buffers to carry the signals out of the CD player (BCK, DATA+DATA-WS) via shielded cables.Previously I was using your suggestion with the Qneg of the FF but it was sometimes ago and I will certainly try again that way. Now BTW I feel in comfort with the XORs, but I would go definitely with single packages.
Bernhard said:
OK I will post something later, or tomorrow.
- Status
- Not open for further replies.