This is probably something of a curiosity but is prompted by a thread originally posted by Andrew Eckhardt that can be found here,
https://www.diyaudio.com/community/threads/phase-shift-pwm.154591/
Rather than necro it I'm going to start an new fail afresh.
Andrew was attempting to do what it says in the title but not having much fun. In the thread newvirus2008 linked to a patent by Nasila also available here,
https://worldwide.espacenet.com/pub...&FT=D&date=20010327&CC=US&NR=6208216B1&KC=B1#
I actually tried doing something like this back in 1986 using a 4046 when my knowledge was less than it is now. I had managed to use a 4046, with some help from Horrowitz & Hill, to implement a audio frequency counter. When Andrew posted his original thread I had returned to the idea but was still beating my head against it and did not respond. However now I am no more clever I'm going to share my thoughts.
This might be a long thread that develops over time. We'll start off with Voltage Mode Control. Then a burble about Loop Compensation. Likely followed by Current Mode Control, Andrew hinted at multiphase operation. Then multiphase operation and bandwidth extension. Controlling, matching, phase currents in multiphase operation and words about coping with overmodulation.
I'm going to be using LTSpice and that includes some hand rolled models so I'll attach them as a zip file. Right click to see the madness inside.
Let's jump in with a switching model of Voltage Mode Cotrol at 500KHz.
This is the startup,
Stabilty is key here. PLLs are hardcore so I'm going to spout words about how the loop in the above circuit is put together. In part that involves a wet finger in the air but in this case the loop is crossing over at FS/PI with FS being the switching frequency of 500KHz so in this case FCO is about 160KHz. kees52 knows of this as being The Nyquist Limit.
Once that is over we get our 1KHz Sine Wave,
And do an FFT on it to see how grim things might be,
The level of grim is -93dB. Of course this is a LTSpice model so in the real world things are likely to be dirt.
Right. That's an introduction. Next up I'll add some words about what the circuit bits are and what they are doing, will be long and may make no sense, and also drop a Linear Model of the loop to demonstrate the loop gain. Also the same for the switching model as described by,
https://ltwiki.org/LTspiceHelpXVII/LTspiceHelp/html/Bode.htm
The title is,
Extracting Switch Mode Power Supply Loop Gain in Simulation and Why You Usually Don't Need To
I kind of disagree with the bit in bold. If you have time to twiddle your thumbs it makes for a great insanity check.
Right! That's it for now. Laterz.
https://www.diyaudio.com/community/threads/phase-shift-pwm.154591/
Rather than necro it I'm going to start an new fail afresh.
Andrew was attempting to do what it says in the title but not having much fun. In the thread newvirus2008 linked to a patent by Nasila also available here,
https://worldwide.espacenet.com/pub...&FT=D&date=20010327&CC=US&NR=6208216B1&KC=B1#
I actually tried doing something like this back in 1986 using a 4046 when my knowledge was less than it is now. I had managed to use a 4046, with some help from Horrowitz & Hill, to implement a audio frequency counter. When Andrew posted his original thread I had returned to the idea but was still beating my head against it and did not respond. However now I am no more clever I'm going to share my thoughts.
This might be a long thread that develops over time. We'll start off with Voltage Mode Control. Then a burble about Loop Compensation. Likely followed by Current Mode Control, Andrew hinted at multiphase operation. Then multiphase operation and bandwidth extension. Controlling, matching, phase currents in multiphase operation and words about coping with overmodulation.
I'm going to be using LTSpice and that includes some hand rolled models so I'll attach them as a zip file. Right click to see the madness inside.
Let's jump in with a switching model of Voltage Mode Cotrol at 500KHz.
This is the startup,
Stabilty is key here. PLLs are hardcore so I'm going to spout words about how the loop in the above circuit is put together. In part that involves a wet finger in the air but in this case the loop is crossing over at FS/PI with FS being the switching frequency of 500KHz so in this case FCO is about 160KHz. kees52 knows of this as being The Nyquist Limit.
Once that is over we get our 1KHz Sine Wave,
And do an FFT on it to see how grim things might be,
The level of grim is -93dB. Of course this is a LTSpice model so in the real world things are likely to be dirt.
Right. That's an introduction. Next up I'll add some words about what the circuit bits are and what they are doing, will be long and may make no sense, and also drop a Linear Model of the loop to demonstrate the loop gain. Also the same for the switching model as described by,
https://ltwiki.org/LTspiceHelpXVII/LTspiceHelp/html/Bode.htm
The title is,
Extracting Switch Mode Power Supply Loop Gain in Simulation and Why You Usually Don't Need To
I kind of disagree with the bit in bold. If you have time to twiddle your thumbs it makes for a great insanity check.
Right! That's it for now. Laterz.
So. Circuit Description.
This is a Phase Locked Loop so naturally we have a Voltage Controlled Oscillator, in this case VCA. This is a hand rolled model that produces a +/-2.5V sin wave output, FO. Its input control range at CTRL is also +/-2.5V and it accepts two parameters, CTR and SPN, such that when CTRL is at 0V the output will be (CTR)Hz, in this case 250KHz. When CTRL is at +2.5V the output is (CTR+SPN)Hz, 500KHz. When CTRL is at -2.5V the output is (CTR+SPN)Hz, 0Hz.. VCA is fed to a digital buffer converting VCA to a square wave also +/-2.5V. VCP is one othe inputs to the Phase Sensitive Detector, PSD, as an Exclusive OR Gate.
The other input to the PSD is RFP. This is derived from REF, a +/-250KHz sin wave via A1 producing another +/-2.5V square wave. As mentioned by Andrew mixing occurs in the PSD so its output, PWP is used, is a 500KHz square wave. This forms the Pulse Width Modulated output and is used to drive the Power Stage, EPOW, and is also fed back to an error amplifier, VEA, configured as an integrator via RPWM and CINT. With the other input, MOD, at 0V this feedback will result in the output of the PSD, PWP, being a 50% duty cycle square wave whose average value is also 0V.
The VC(O)A in conjunction with the PSD behave as an integrator, Phase is the integral of frequency. With the error amplifier, VEA, also acting as an integrator the overall loop is second order and will therefore be unstable. To overcome this RP, CP and RZ insert a phase bump in the loop to render it first order at the loop crossover frequency and therefore stable. However we have to determine what that crossover frequency is which might involve some hard thinking or some tricky thinking so we cheat.
Now it is a known thing that in a switch mode power supply, in this case a buck convertor operated with continuous inductor current that the maximum crossover frequency will be FS/PI. FS in this case is 500KHz so our crossover target will be about 160KHz. The VCO is already set to its maximum gain so now we have to think about the maximum gain we might get from the error amplifier, VEA. This occurs when the ripple at its output matches the input control range, CRTL, of VCA or +/-2.5V. The zero demand output of the VEA is a triangle wave so we just select RPWM and CINT to produce a +/-2.5V triangle wave from a +/-2.5V 50% duty cycle 500KHz square wave.
Almost Job Done.
Now we have to put the Phase Bump at the right frequency in this case the target crossover frequency of 160KHz. For the component values chosen for RP and CZ this occurs when the impedance of CP is 1K35 at that frequency. That gives us CZ as 730p so pick 750p and feel really embarrased that I have actually used 560p. Minor Brane Fart.
Next up I'll introduce the analog model of the loop showing how things are, supposedly, working out in the way the words are saying they are.
Just to tidy up here is the start up when I change CZ to 750p,
Now it is less wibbly wobbly or rather critically damped.
This is a Phase Locked Loop so naturally we have a Voltage Controlled Oscillator, in this case VCA. This is a hand rolled model that produces a +/-2.5V sin wave output, FO. Its input control range at CTRL is also +/-2.5V and it accepts two parameters, CTR and SPN, such that when CTRL is at 0V the output will be (CTR)Hz, in this case 250KHz. When CTRL is at +2.5V the output is (CTR+SPN)Hz, 500KHz. When CTRL is at -2.5V the output is (CTR+SPN)Hz, 0Hz.. VCA is fed to a digital buffer converting VCA to a square wave also +/-2.5V. VCP is one othe inputs to the Phase Sensitive Detector, PSD, as an Exclusive OR Gate.
The other input to the PSD is RFP. This is derived from REF, a +/-250KHz sin wave via A1 producing another +/-2.5V square wave. As mentioned by Andrew mixing occurs in the PSD so its output, PWP is used, is a 500KHz square wave. This forms the Pulse Width Modulated output and is used to drive the Power Stage, EPOW, and is also fed back to an error amplifier, VEA, configured as an integrator via RPWM and CINT. With the other input, MOD, at 0V this feedback will result in the output of the PSD, PWP, being a 50% duty cycle square wave whose average value is also 0V.
The VC(O)A in conjunction with the PSD behave as an integrator, Phase is the integral of frequency. With the error amplifier, VEA, also acting as an integrator the overall loop is second order and will therefore be unstable. To overcome this RP, CP and RZ insert a phase bump in the loop to render it first order at the loop crossover frequency and therefore stable. However we have to determine what that crossover frequency is which might involve some hard thinking or some tricky thinking so we cheat.
Now it is a known thing that in a switch mode power supply, in this case a buck convertor operated with continuous inductor current that the maximum crossover frequency will be FS/PI. FS in this case is 500KHz so our crossover target will be about 160KHz. The VCO is already set to its maximum gain so now we have to think about the maximum gain we might get from the error amplifier, VEA. This occurs when the ripple at its output matches the input control range, CRTL, of VCA or +/-2.5V. The zero demand output of the VEA is a triangle wave so we just select RPWM and CINT to produce a +/-2.5V triangle wave from a +/-2.5V 50% duty cycle 500KHz square wave.
Almost Job Done.
Now we have to put the Phase Bump at the right frequency in this case the target crossover frequency of 160KHz. For the component values chosen for RP and CZ this occurs when the impedance of CP is 1K35 at that frequency. That gives us CZ as 730p so pick 750p and feel really embarrased that I have actually used 560p. Minor Brane Fart.
Next up I'll introduce the analog model of the loop showing how things are, supposedly, working out in the way the words are saying they are.
Just to tidy up here is the start up when I change CZ to 750p,
Now it is less wibbly wobbly or rather critically damped.
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Next up. The Analog Model. This one demonstates the systems loop gain.
On the left our Voltage Error Amplifier, as before. The loop is broken with an AC source, as per Middlebrook. Followed by the Phase Bump Network. Now we get the VCO as a Voltage Controlled Current Source, GVCO, driving a capacitor, CVCO, to implement the Frequency/Phase integration. This is followed by a Voltage Controlled Voltage Source, EPSD, to represent the Phase Sensitive Detector.
Gain in GVCO is set to 4.PI.SPN/5. 1Hz is 2PI Radians. The control range is 5V. Over 5V the frequency changes by 2SPN. Gain in EPSD is set to 5/PI. For an Exclusive OR gate the output changes by its supply (+/-2.5V) over a 90 degree phase shift in its inputs.
Then we plot V(a)/V(b). Crossover occurs at about 160KHz with 42 degrees of Phase Margin. Close to what we expected or wanted..
New zip of models attached.
Next up Current Mode Control.
On the left our Voltage Error Amplifier, as before. The loop is broken with an AC source, as per Middlebrook. Followed by the Phase Bump Network. Now we get the VCO as a Voltage Controlled Current Source, GVCO, driving a capacitor, CVCO, to implement the Frequency/Phase integration. This is followed by a Voltage Controlled Voltage Source, EPSD, to represent the Phase Sensitive Detector.
Gain in GVCO is set to 4.PI.SPN/5. 1Hz is 2PI Radians. The control range is 5V. Over 5V the frequency changes by 2SPN. Gain in EPSD is set to 5/PI. For an Exclusive OR gate the output changes by its supply (+/-2.5V) over a 90 degree phase shift in its inputs.
Then we plot V(a)/V(b). Crossover occurs at about 160KHz with 42 degrees of Phase Margin. Close to what we expected or wanted..
New zip of models attached.
Next up Current Mode Control.
I played with the CD4046 a bunch in college, trying to make a guitar synth, as they were all the rage at the time. It got me a good upgrade to my GPA, as the EE prof I was working with in the elective course liked what I was doing.
I can only recall that the XOR gate phase lock controller made PWM, which was in proportion to how far the phase difference was between the input signal and the oscillator signal chasing it. It did make for some otherwise unheard of sounds, when the input signal took an octave jump, with the loop severely damped so it took time for it to glide up to the new frequency.
I always used the other phase lock controller in it, the "phase comparitor II" with the state-space diagram I never worked through. I do recall if fin<fosc, the output would be pulled to Vdd; fin>fosc, output pulled to Vcc and fin=fosc the output would go tristate. I introduced my own tri-state element via a CD 4013 analog switch, hoping to hold the oscillator frequency to a note via foorswitch or the envelope crossing a low threshold. It worked sometimes, but not good enough to play music.
I can imagine if one could get a 50% duty cycle at a phase locked condition, then perturb the VCO with audio, the PWM would bounce around 50% in response, then quickly settle back when the perturbation went away. I recall the output of the XOR was some pulse in lock, but not 50%.
One of the things I never addressed, but wanted to, was how to make the VCO glide up to get in lock with the input signal linear, as it was not being a RC basically. I had transconductance amplifiers available at the time (CA3080) but was not smart enough to graft those onto the tri-state output, such that it drives + current in the high state, - current in the low state and no current in tri-state.
I also tried to make the "damping" resistor into the same function as a LFO modulation wheel on a synth, but, while it did it, it wasnt particularly musical. Finally, because I naively operated the device at only a +Vcc, the high-side fet and low side fet of the phase comparitor "II" output didnt pull the cap charge of the VCO voltage control input up and down at the same rate. I didnt try tying the (-) of that cap to Vcc/2, which I did years and years later to get that symmetrical behavior.
One of the last things I worked on at Intel was this overshoot / undershoot quenching circuit, which had the same problem if only in simulation. When the current stepped on, the converter voltage would undershoot and I could catch that with a pulse through a FET and inductor to +12V VCC. When the current stepped off, I could do the same with another FET to ground, but it wasnt as effective for some reason. The converter output voltage was, say, 1.5V.
So the high side FET had a lot more voltage difference to work with. Deciding it needed a negative voltage, made the idea work symmetrically. Server power systems dont have a high current negative supply and they werent about to provide one for some 'shoot quenching circuit to work. The guy I was working with retired, we thought about a patent with his boss, then I changed departments, then they closed the place. So that's where that idea ended up.
Good luck with your PLL based audio modulator.
I can only recall that the XOR gate phase lock controller made PWM, which was in proportion to how far the phase difference was between the input signal and the oscillator signal chasing it. It did make for some otherwise unheard of sounds, when the input signal took an octave jump, with the loop severely damped so it took time for it to glide up to the new frequency.
I always used the other phase lock controller in it, the "phase comparitor II" with the state-space diagram I never worked through. I do recall if fin<fosc, the output would be pulled to Vdd; fin>fosc, output pulled to Vcc and fin=fosc the output would go tristate. I introduced my own tri-state element via a CD 4013 analog switch, hoping to hold the oscillator frequency to a note via foorswitch or the envelope crossing a low threshold. It worked sometimes, but not good enough to play music.
I can imagine if one could get a 50% duty cycle at a phase locked condition, then perturb the VCO with audio, the PWM would bounce around 50% in response, then quickly settle back when the perturbation went away. I recall the output of the XOR was some pulse in lock, but not 50%.
One of the things I never addressed, but wanted to, was how to make the VCO glide up to get in lock with the input signal linear, as it was not being a RC basically. I had transconductance amplifiers available at the time (CA3080) but was not smart enough to graft those onto the tri-state output, such that it drives + current in the high state, - current in the low state and no current in tri-state.
I also tried to make the "damping" resistor into the same function as a LFO modulation wheel on a synth, but, while it did it, it wasnt particularly musical. Finally, because I naively operated the device at only a +Vcc, the high-side fet and low side fet of the phase comparitor "II" output didnt pull the cap charge of the VCO voltage control input up and down at the same rate. I didnt try tying the (-) of that cap to Vcc/2, which I did years and years later to get that symmetrical behavior.
One of the last things I worked on at Intel was this overshoot / undershoot quenching circuit, which had the same problem if only in simulation. When the current stepped on, the converter voltage would undershoot and I could catch that with a pulse through a FET and inductor to +12V VCC. When the current stepped off, I could do the same with another FET to ground, but it wasnt as effective for some reason. The converter output voltage was, say, 1.5V.
So the high side FET had a lot more voltage difference to work with. Deciding it needed a negative voltage, made the idea work symmetrically. Server power systems dont have a high current negative supply and they werent about to provide one for some 'shoot quenching circuit to work. The guy I was working with retired, we thought about a patent with his boss, then I changed departments, then they closed the place. So that's where that idea ended up.
Good luck with your PLL based audio modulator.
Here's Current Mode Control.
You do Current Mode Control in order to reduce the order of the Output Filter. An LC section is Second Order. If you measure and control the current in the output inductor, LFILT, then you end up with a Current Source driving the output capacitor, CFILT, which is a first order response. You also, might or will, want this because, as Andrew has suggested, PWM based on a PLL lends itself to MultiPhase operation. One of the problems with MultiPhase operation is that if you do not control the individual phase currents then, without introducing power wasting parasitic resistances, the phase currents will not match and things can go rapidly Horror Show.
Not much has changed. However the Voltage Error Amplifier, VEA, has become a Current Error Amplifier and it is no longer an integrator. This is because the integration is now occuring in the output inductor, LFILT. A square wave voltage across an inductor becomes a triangle wave, ripple current in that inductor.
Now we are measuring that with Behavioural Source, ILF, bottom right. It is set up to mimic a 50mR resistor. Inductors integrate the Volt/Seconds applied to them and again our target is a +/-2.5V triangle wave at the output of what has now become the Current Error Amplifier, CEA.
When MOD is zero we apply a +/-50V 500KHz 50% duty cycle square wave across LFILT. Each way it is 50V for 1uS across 16uH. Change in current in the inductor is Vin.Ton/L or 50.1u/16u or 3.125A converted to 0.15625 volts across our 50mR sense resistor. In order to swing 5V (+/-2.5V) at the output of the CEA it needs a gain of 5/0.15625 or 32 so we kind of make it so. RILF and RMOD become 1K with RCGA being 30K. Setting MOD to 0,6V is 0.6/50mR or 12A giving 48V across a 4R load.
Start up is,
We've lost some phase margin due to my inexact science but it works. I shall belatedly mention that the output of the CEA is indeed a maximum of +/-2.5V as we wanted. This is our 1KHz sin wave after things have settled down,
Looks similar to the Voltage Mode Control example. And the FFT of VOUT,
Is a dissapointment and I cannot explain why so, for the moment I am not going to chase it.
You do Current Mode Control in order to reduce the order of the Output Filter. An LC section is Second Order. If you measure and control the current in the output inductor, LFILT, then you end up with a Current Source driving the output capacitor, CFILT, which is a first order response. You also, might or will, want this because, as Andrew has suggested, PWM based on a PLL lends itself to MultiPhase operation. One of the problems with MultiPhase operation is that if you do not control the individual phase currents then, without introducing power wasting parasitic resistances, the phase currents will not match and things can go rapidly Horror Show.
Not much has changed. However the Voltage Error Amplifier, VEA, has become a Current Error Amplifier and it is no longer an integrator. This is because the integration is now occuring in the output inductor, LFILT. A square wave voltage across an inductor becomes a triangle wave, ripple current in that inductor.
Now we are measuring that with Behavioural Source, ILF, bottom right. It is set up to mimic a 50mR resistor. Inductors integrate the Volt/Seconds applied to them and again our target is a +/-2.5V triangle wave at the output of what has now become the Current Error Amplifier, CEA.
When MOD is zero we apply a +/-50V 500KHz 50% duty cycle square wave across LFILT. Each way it is 50V for 1uS across 16uH. Change in current in the inductor is Vin.Ton/L or 50.1u/16u or 3.125A converted to 0.15625 volts across our 50mR sense resistor. In order to swing 5V (+/-2.5V) at the output of the CEA it needs a gain of 5/0.15625 or 32 so we kind of make it so. RILF and RMOD become 1K with RCGA being 30K. Setting MOD to 0,6V is 0.6/50mR or 12A giving 48V across a 4R load.
Start up is,
We've lost some phase margin due to my inexact science but it works. I shall belatedly mention that the output of the CEA is indeed a maximum of +/-2.5V as we wanted. This is our 1KHz sin wave after things have settled down,
Looks similar to the Voltage Mode Control example. And the FFT of VOUT,
Is a dissapointment and I cannot explain why so, for the moment I am not going to chase it.
The XOR, in lock, does produce a 50% duty cycle square wave for the conditions given in my mumble. A 50% duty cycle square wave, with equal +/- amplitude averages to zero. If you disturb it with a modulation signal then you get a PWM ouput.
If you were operating your 4046 on a unipolar supply, 15V?, then you would get 50% duty cycle with the input to the VCO at 7.5V, give or take.
Without checking the CD4046 came with an Exclusive OR gate and, at least, an SR Phase/Frequency detector. It may have also come with the Charge Pump Tri State one. The HC/HCT version definitely came with all three. The Charge Pump one is used to minimise ripple at the input to the VCO which reduces spurs but for PWM you can't avoid the ripple.
Even so for PWM, with adjustments for gain of the PSD and subsequently, you can use practically any phase detector. They just don't give their supposed benefit because they will still ripple. As I see things, the ripple will always be there so the XOR kind of wins, perhaps, apart from dealing with overmodulation, and even so it still does.
Being a rubbish Guitar Player myself I have no idea how a 4046 would make me better. And then they killed the CA3080.
Fortunately Audio is strictly symetrical so you can set as fast as you reset. VRMS are not unless, perhaps, you make them so but that is another whole cost benefit analysis and by the time you get the power to the die you may as well be dead. That's Evil Bad Lands.
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Oh. I forgot the zip. A little bit of renaming going on because I was so well prepared to blow chunks.
Hmm. Another oversight on my part. The performance under Current Mode Control was dissapointing because the 4R load messes with things at low frequency. We can see that in an Analog model of the current loop. With the parallel resistance for CFILT set to 4R the result is this,
Setting the parallel resistance to 1u gives us this,
Which now matches the Voltage Loop. Making that change in the Switching model gives this as the FFT for I(LFILT),
Of course we don't get to do this in real life without cryogenic loudspeakers.
Updated LTSpice files attached.
Next post will look at Post Filter Feedback. I'll be ignoring the Voltage Mode Control example and wrapping another Voltage Error Amplifier, Output Error Amplifier, around the Current Mode Control example. This may involve Dragons.
Setting the parallel resistance to 1u gives us this,
Which now matches the Voltage Loop. Making that change in the Switching model gives this as the FFT for I(LFILT),
Of course we don't get to do this in real life without cryogenic loudspeakers.
Updated LTSpice files attached.
Next post will look at Post Filter Feedback. I'll be ignoring the Voltage Mode Control example and wrapping another Voltage Error Amplifier, Output Error Amplifier, around the Current Mode Control example. This may involve Dragons.
And Dragons there were. I was working on this some time ago and kind of gave up. In the time between I've forgotton some of the things I did to get a, possibly still unsatifactory,result.
So ignoring the Dragons, until they flame me out. In the Current Mode Control model our current sense element was a 50mR equivalent so it would ideally provide 20A/V for 1V demand. RILF and RMOD are the same. That should be more than enough to drive a 4R load apart from speakers not being pure resistances. Also, if we in some way clamp that demand signal, then we get a natural current limit.
Again this is a current source driving the output filter capacitor, -20dB/DEC, so in fantasy land the system hits 0dB, 1V out for 1V in, when the capacitor's impedence is also 50mR. 1/2PIRC or 3183099Hz. Of course the loop, driving a short circuit, runs out of steam at 160KHz so let's target a 80KHz voltage loop crossover. This lets us guess the gain in our Voltage Output Amplifier as being 80K/318K or 0.0251.
Using an inverting configuration with a 39K feedback resistor from the output gives our local feedback resistor as 980R. Now we break the local loop with a capacitor in series with that feedback resistor to boost the low frequency gain and place the zero at 40KHz. That's about 3n9. Things now look like this.
And it does this.
Life is so unfair.
There are two reasons for this and maybe more that I cannot wave a hand at.
The first one is that we are using a Phase Locked Loop and if it is not locked we have a nothing. This is V(cea) flapping up and down at the begining. If it is not locked then the current loop is not working so the voltage loop has nothing to control. The second one is that, in this case, the functioning of the current loop is also strongly influenced by what is is driving.
This Current Mode Control stuff is all well and good for a Switch Mode Power Supply when the loop has a nice big and meaty low ESR output filter capacitor to chomp on. A Class D amplifier does not give you that and, as noted before, that really messes up the loop performance. Remember I had to use a short circuit to get the Voltage and Current models to match each other.
Using Cunning Plan A I reduce the load to 2R.
And we get this.
The CEA still has to get into lock but now it has a little bit more to bite on it does manage it and once the current loop is operational we get our 1KHz, 39V, sine wave.
YAY1!1 Unfortunately it is still DIRT but I might be back.
So ignoring the Dragons, until they flame me out. In the Current Mode Control model our current sense element was a 50mR equivalent so it would ideally provide 20A/V for 1V demand. RILF and RMOD are the same. That should be more than enough to drive a 4R load apart from speakers not being pure resistances. Also, if we in some way clamp that demand signal, then we get a natural current limit.
Again this is a current source driving the output filter capacitor, -20dB/DEC, so in fantasy land the system hits 0dB, 1V out for 1V in, when the capacitor's impedence is also 50mR. 1/2PIRC or 3183099Hz. Of course the loop, driving a short circuit, runs out of steam at 160KHz so let's target a 80KHz voltage loop crossover. This lets us guess the gain in our Voltage Output Amplifier as being 80K/318K or 0.0251.
Using an inverting configuration with a 39K feedback resistor from the output gives our local feedback resistor as 980R. Now we break the local loop with a capacitor in series with that feedback resistor to boost the low frequency gain and place the zero at 40KHz. That's about 3n9. Things now look like this.
And it does this.
Life is so unfair.
There are two reasons for this and maybe more that I cannot wave a hand at.
The first one is that we are using a Phase Locked Loop and if it is not locked we have a nothing. This is V(cea) flapping up and down at the begining. If it is not locked then the current loop is not working so the voltage loop has nothing to control. The second one is that, in this case, the functioning of the current loop is also strongly influenced by what is is driving.
This Current Mode Control stuff is all well and good for a Switch Mode Power Supply when the loop has a nice big and meaty low ESR output filter capacitor to chomp on. A Class D amplifier does not give you that and, as noted before, that really messes up the loop performance. Remember I had to use a short circuit to get the Voltage and Current models to match each other.
Using Cunning Plan A I reduce the load to 2R.
And we get this.
The CEA still has to get into lock but now it has a little bit more to bite on it does manage it and once the current loop is operational we get our 1KHz, 39V, sine wave.
YAY1!1 Unfortunately it is still DIRT but I might be back.
Another slight oversight. I did not include words about the liear model of the loop for post filter Voltage Mode Feedback wrapped around a Current Mode Control Loop. The words in my last post about this did include the methed used to calculate, guess, the compensation components for the switch model. Here's the analog model with the values as previously suggested.
Plotting V(c)/V(d) gives the loop gain as
Crossover at about 90KHz with 83 degrees phase margin. This is with the load set to 2R. 10K, or open circuit gives this.
and we are in trouble. In the first instance because the loop is not going to lock so that is game over. In the second instance because the above is simply not stable.
Of course the most obvious solution is to drop the gain in the Voltage loop and accept poorer performance. Now there may be other methods, to be covered later, that almost save us from this but what we really really want is to try out multiphase operation!1!.
Updated folder attached.
Plotting V(c)/V(d) gives the loop gain as
Crossover at about 90KHz with 83 degrees phase margin. This is with the load set to 2R. 10K, or open circuit gives this.
and we are in trouble. In the first instance because the loop is not going to lock so that is game over. In the second instance because the above is simply not stable.
Of course the most obvious solution is to drop the gain in the Voltage loop and accept poorer performance. Now there may be other methods, to be covered later, that almost save us from this but what we really really want is to try out multiphase operation!1!.
Updated folder attached.
Let's Go Multiphase
Having failed to properly fix the previous issues, that's boring, here is how you go multiphase. The non cunning plan would be to implement multiple Phase Locked loops and phase shift the reference clocks. Unless you are already bald you would rip your hair out. The other cunning plan would be this.
Here we are still using a single Phase Locked Loop but we set its VCO center and span frequency to a higher value and do the same to the Reference Frequency, REF. Then we use a pair of Ring Shift Registers, RING0 and RING1, with negative feedback from the final tap to divide those frequencies down and generate our four phases of Pulse Width Modulation with four Exclusive OR Gates, PSA-PSD PAP-PDP. These then drive our four power stages, EPA-EPD, with the inductor currents being summed to the output, OUT. We need to CLP these registers to a state of sense to begin.
The other invisible fudge is we need to give our output inductors some series resistances so they will current share. I know. Its grim but there may aso be a solution to that one.
There is an inherent divide by two in the Rings so REF and CTR become 2000K to operate each phase at the original 500KHz. The apparent switching frequency becomes 2MHz and, as such we might expect 4 times the loop bandwidth. 2E6/PI or 636KHz. That means we have to recompensate the loop. This time the current feedback elements are modelled as current sources ILA-ILD to allow easy summing at the CEA input via SUM. The scaling is equivalent to a 1K resistor per output so now we have four of them. 250R, we get four times the loop bandwidth?
Oh no we don't? The loop is nominally second order so for four times the loop crossover frequency we need sixteen times the loop gain, SQRT(16)=4, so we change RCGA from 30K to 120K to get the extra. We should also be bothered about the gain bandwidth product of the CEA. Then we adjust CP to place the phase bump at about 636K or divide it by four to get 180p.
Does it work?
Ignoring possible collateral pain elsewhere it seems to doe the job. Remember that the orginal goal for achieving maximum loop gain was to set the gain in the CEA to a level such that ripple at its output matched the control range of the VCO OR +/-2.5V. We have one of those. Now the CEA output looks like a bunch of Kilrathi SpaceShips. This is what MultiPhase Converters do. Rather than a single Minima at 100% modulation you get more and even more as you add phases. Just tag some more D-flops in your rings, famous last words.
You can see this more clearly in the bottom plot for ((Cfilt). Have a Google for Multiphase VRM. Otherwise the phase inductor currents are tracking each other. They should because we toileted on them by adding series resistance but if the loop was not working properly they would be an absolute mess.
The FFT of V(out)
Again it might be slightly dissapointing but we are operating at 2MHz and there is the caveat that it is working into a 4R load rather than a short circuit. Remember the 500KHz single phase performance from.
https://www.diyaudio.com/community/...th-modulation-a-curiosity.398911/post-7341661
Along with the additional hash we appear to have dropped the distortion by 40dB. I have no idea.
Usual update of the folder.
Having failed to properly fix the previous issues, that's boring, here is how you go multiphase. The non cunning plan would be to implement multiple Phase Locked loops and phase shift the reference clocks. Unless you are already bald you would rip your hair out. The other cunning plan would be this.
Here we are still using a single Phase Locked Loop but we set its VCO center and span frequency to a higher value and do the same to the Reference Frequency, REF. Then we use a pair of Ring Shift Registers, RING0 and RING1, with negative feedback from the final tap to divide those frequencies down and generate our four phases of Pulse Width Modulation with four Exclusive OR Gates, PSA-PSD PAP-PDP. These then drive our four power stages, EPA-EPD, with the inductor currents being summed to the output, OUT. We need to CLP these registers to a state of sense to begin.
The other invisible fudge is we need to give our output inductors some series resistances so they will current share. I know. Its grim but there may aso be a solution to that one.
There is an inherent divide by two in the Rings so REF and CTR become 2000K to operate each phase at the original 500KHz. The apparent switching frequency becomes 2MHz and, as such we might expect 4 times the loop bandwidth. 2E6/PI or 636KHz. That means we have to recompensate the loop. This time the current feedback elements are modelled as current sources ILA-ILD to allow easy summing at the CEA input via SUM. The scaling is equivalent to a 1K resistor per output so now we have four of them. 250R, we get four times the loop bandwidth?
Oh no we don't? The loop is nominally second order so for four times the loop crossover frequency we need sixteen times the loop gain, SQRT(16)=4, so we change RCGA from 30K to 120K to get the extra. We should also be bothered about the gain bandwidth product of the CEA. Then we adjust CP to place the phase bump at about 636K or divide it by four to get 180p.
Does it work?
Ignoring possible collateral pain elsewhere it seems to doe the job. Remember that the orginal goal for achieving maximum loop gain was to set the gain in the CEA to a level such that ripple at its output matched the control range of the VCO OR +/-2.5V. We have one of those. Now the CEA output looks like a bunch of Kilrathi SpaceShips. This is what MultiPhase Converters do. Rather than a single Minima at 100% modulation you get more and even more as you add phases. Just tag some more D-flops in your rings, famous last words.
You can see this more clearly in the bottom plot for ((Cfilt). Have a Google for Multiphase VRM. Otherwise the phase inductor currents are tracking each other. They should because we toileted on them by adding series resistance but if the loop was not working properly they would be an absolute mess.
The FFT of V(out)
Again it might be slightly dissapointing but we are operating at 2MHz and there is the caveat that it is working into a 4R load rather than a short circuit. Remember the 500KHz single phase performance from.
https://www.diyaudio.com/community/...th-modulation-a-curiosity.398911/post-7341661
Along with the additional hash we appear to have dropped the distortion by 40dB. I have no idea.
Usual update of the folder.
Last edited:
Minor update with the linear model for 4Phase operation.
The circuit,
The loop gain,
We were expecting a crossover of 630K but we don't hit that target. In fact the figures are always slightly low which I will attribute to either compnent selction to closest standard values or the nature of the phase bump network. It's within 10% so that will do.
We also have to be careful how we attribute gains. In the above GVCO has not been adjusted to its 2MHz equivalent. Neither has the current sense element or the error amplifier input resistance. What has been changed is the inductance value, 4 times 16u in parallel is 4u, and the feedback resistor in the error amplifier, 32K[30K] -> 130K[128K]. More hand wringing might be needed to explain that one but this is how I see it.
Again we should be concerned about the gain bandwidth product of that amplifier and the other fallover point, for any external voltage loop, will be the performance of the output filter.
The circuit,
The loop gain,
We were expecting a crossover of 630K but we don't hit that target. In fact the figures are always slightly low which I will attribute to either compnent selction to closest standard values or the nature of the phase bump network. It's within 10% so that will do.
We also have to be careful how we attribute gains. In the above GVCO has not been adjusted to its 2MHz equivalent. Neither has the current sense element or the error amplifier input resistance. What has been changed is the inductance value, 4 times 16u in parallel is 4u, and the feedback resistor in the error amplifier, 32K[30K] -> 130K[128K]. More hand wringing might be needed to explain that one but this is how I see it.
Again we should be concerned about the gain bandwidth product of that amplifier and the other fallover point, for any external voltage loop, will be the performance of the output filter.
Last edited: