"I brake for tutorials" 😀
Thank you for another great article! It perfectly makes up with the hint you gave me in this F5 Mosfet mismatch matter a few days ago. Once again a real eye-opener to me! 🙂
Thank you for another great article! It perfectly makes up with the hint you gave me in this F5 Mosfet mismatch matter a few days ago. Once again a real eye-opener to me! 🙂
Thanks for the interesting paper. Makes it seem easy. Now If I could only remember it all when I put it down. So you tweak every amplifier with a distortion analyzer before it goes out the door?
Thanx Nelson... haven't finished reading it yet, but it set some neurons off...
Page 3, paragraph 4 -- i don't think you intended on saying common-drain twice.
dave
Page 3, paragraph 4 -- i don't think you intended on saying common-drain twice.
dave
Since we are on the topic of editing.
On the bottom of page 9 there is a sentence that doesn't read so well. I am not sure if there is a comma missing or a word or so missing.
"Depending on the dimensions of the Gate structure on the chip can exhibit pentode or triode characteristics, or an in-between “mixed mode”."
Should it read "Depending on the dimensions of the Gate structure on the chip, the chip can exhibit pentode or triode characteristics, or an in-between "mixed mode"."
On the bottom of page 9 there is a sentence that doesn't read so well. I am not sure if there is a comma missing or a word or so missing.
"Depending on the dimensions of the Gate structure on the chip can exhibit pentode or triode characteristics, or an in-between “mixed mode”."
Should it read "Depending on the dimensions of the Gate structure on the chip, the chip can exhibit pentode or triode characteristics, or an in-between "mixed mode"."
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If I am not mistaken reading the sweet spot article, as mentioned by Nelson, the valve/tube designers knew about this in the earlier 1930's by applying the Load Line Technique to obtain the minimum distortion and obtain the maximum output swing from the anode for a common cathode tube configuration. This can be obtained by selecting the correct bias point, anode voltage and loading resistor. I learned about this during my undergraduate during the seventies, no one teach this now.
This technique can also be applied to Jfet as well as pointed out by Nelson in the Jfet Boz project.
Cheers.
This technique can also be applied to Jfet as well as pointed out by Nelson in the Jfet Boz project.
Cheers.
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