Stereo DAC with digital PLL

[t_majerovic]

Hi all

I'm going to design and build my own DAC. Here design ideas:
-receiver CS8416 is configured to slave and software mode
-digital audio data bus is configured to I2S
-CS2100 generates low jitter system clock for audio DACs
-counter 4024 generates signals BIT_CLK (FSx64) WORD_CLK (FS)
-D flip-flops synchronize all I2S signals with system clock
-each audio channel has own DAC PCM1794a configured to I2S mono mode
-I/V conversion will deliver two audio transformers connected to DACs outputs (it is not in schematics)
-CS8416 and CS2100 are controlled over I2C by PIC16F883 (it uses internal oscillator and PIC is alive only when port B changes logical value interrupt from CS8416, CS2100 PLL unlock or change over user interface)
-power supply uses low noise voltage controllers. Critical devices have own voltage controller to avoid noise from other devices.

Here is schematics.
Picasa Web Albums - tomas.majerovic - DAC

All your comments are appreciated.

Tomas

 

[kevinkr]

Take a look at the Wolfson WM8804/8805 SPDIF receivers, they have very good clock recovery and probably offer less jitter than your CS8416 and CS2100 combination.

I use a WM8804 with mono mode I2S PCM1794A into THS4131 driving transformers in my dac. The only problem is in hardware mode WM8804 will not do 176kHz bit rate.. (no such limitation in software mode!) Mine is loosely based on some bare boards and a SPDIF receiver PCB purchased from TPA.