SPDIF balanced output

stormsonic

Member
I've done this already but get crazy figures:
High-Level Output Voltage, VOH IO = –30mA VDD–0.7(min) VDD–0.4(typ) VDD(Max)
Low-Level Output Voltage, VOL IO = +30mA 0(min) 0.4(typ) 0.7(max)

I (mA) V R (ohm)
30 4.6 153.333333 for High
30 0.4 13.333333 for Low

So 83 ohm but this seems too high, no? I think I heard 20 to 30 mentioned somewhere as a reasonable figure?

What's wrong with my technique above?

Think again for high. On output you have between 0.4V - 0.7V voltage drop and current through is 30mA, what is resistance?

jkeny

Banned
Ok, sorry I was taking the absolute voltage (5-0.4) in this case not the drop so I now have

30 0.7 = 23ohm
30 0.4 = 13ohm

So somewhere between 13 & 23 ohm
Average = 18ohm
That's better - sound about right?

But this is a pretty broad range & trying to match exactly to 75ohm for minimum reflections, every ohm counts so...............

Should my other voltage divider technique not give me a better reading than this? I'm always reluctant to take datasheet values at face value A cross-check would be no harm, no?

I can't see what's wrong with the technique (but patently I'm no expert) - the voltage through a resistor (the Zout) will be halved if an equal resistor is used in a voltage divider (my potentiometer)? This would normally work to ground so I'm just wondering how this can be used in a balanced configuration?

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stormsonic

Member
Yes, 18R is rough estimate, just to calculate. Output should be checked and measured anyway.

Will not comment your measuring technique. Just try with potentiometer. Or with more potentiometers with different values

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jkeny

Banned
Yes, 18R is rough estimate, just to calculate. Output should be checked and measured anyway.
Ok, how would you measure this?

Will not comment your measuring technique. Just try with potentiometer. Or with more potentiometers with different values
Why no comment? Is a pot too insensitive for this fine a measurement? Should I be trying different fixed R's instead?

I presume the problem is going to be that the voltage is so low that an accurate measure of it is difficult & half that is more difficult again.

What would be a better, more accurate method of measuring this Zout?

Seeing as this is a differential output stage should I be using the pot (or R) to ground to measure Zout on each leg? I know these are probably basic questions but I'm confused. Thanks for your help so far

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stormsonic

Member
Joseph K posted nice pictures of measurement setup LINK
you need fast scope or TDR. You need to see things, with multimeter you can't do this.

Multimeter is wrong tool for this job, it is like asking, how to solder/desolder resistor with a spoon.
Potentiometer can be used on RX side or TX side, but you need to see waveform.

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abraxalito

Member
I want to investigate the possibility of using a differential SPDIF line driver on the output of a device to:
- eliminate the need for a SPDIF output transformer as these require all sorts of contortion to get them right & I don't have the equipment or time or knowledge to do so.

I realise I'm a couple of days late to the party, but anyway... How does differential eliminate the need for an output transformer? Quite a few SPDIF circuits (single ended) I've seen don't have transformers, just resistive pads.

- provide a purely resistive 75ohm load to the DIT for better impedance matching rather than the inductive/reactive load that a SPDIF transformer presents.

A transformer's impedance will be in parallel with the source resistance, and its best if its inductance is fairly high (say >0.5mH or so). So that won't affect the resistance very much within the band of interest. Maybe around the same as sending the signal through an RCA (not a good impedance match compared with a BNC).

I'm using a DIT4196 Digital transmitter which has differential output line drivers. I'm not talking about AES, 110ohm balanced, I still want to use existing SPDIF 75 ohm cabling & the DAC will have standard SPDIF input circuitry - transformer receiver, etc.

Can't figure out why you want to send a differential signal down unbalanced cabling

Would I lose out on the common mode noise rejection if not having twisted pair?

Definitely. The point of balanced cabling is that interfering signals affect both signal lines approximately equally. That's why coax isn't generally used to transmit balanced signals.

How much of a drawback would this be?

Depends on various factors like the CMRR of the receiving circuit, the amount of noise in the environment...

Firstly, why isn't this done more often?

For the reasons pointed out above - deliberately unbalancing a balanced signal takes away almost all the benefits of running balanced.

Am I missing something?

From here, it does indeed look like you are missing something rather big, yes. Like a rhinoceros in the room.

jkeny

Banned
Thanks Stormsonic!!

jkeny

Banned
I realise I'm a couple of days late to the party, but anyway... How does differential eliminate the need for an output transformer? Quite a few SPDIF circuits (single ended) I've seen don't have transformers, just resistive pads.
It provides galvanic isolation without the need for a transformer that is difficult to get right - good LF performance & high speed signal passing are a difficult ask.

A transformer's impedance will be in parallel with the source resistance, and its best if its inductance is fairly high (say >0.5mH or so). So that won't affect the resistance very much within the band of interest. Maybe around the same as sending the signal through an RCA (not a good impedance match compared with a BNC).
I think you might find that lowest leakage inductance is what you want for SPDIF transformer. Stormsonic can tell you about this. DO you know all the tricks to get these SPDIF transformers looking right on a TDR - maybe not?

Can't figure out why you want to send a differential signal down unbalanced cabling

Definitely. The point of balanced cabling is that interfering signals affect both signal lines approximately equally. That's why coax isn't generally used to transmit balanced signals.
Well it may make some difference to common mode noise cancelling but this is not why I'm doing it.

Depends on various factors like the CMRR of the receiving circuit, the amount of noise in the environment...

For the reasons pointed out above - deliberately unbalancing a balanced signal takes away almost all the benefits of running balanced.
The cabling does not make the signal balanced & doesn't unbalance it either! Galvanic isolation which maybe worthwhile & in this instance perhaps more important as this is also USB

From here, it does indeed look like you are missing something rather big, yes. Like a rhinoceros in the room.
Maybe, but aren't these protected species so stop taking pot shots !

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abraxalito

Member
It provides galvanic isolation without the need for a transformer that is difficult to get right - good LF performance & high speed signal passing are a difficult ask.

In my understanding, galvanic isolation means complete isolation at DC. But merely having a differential output won't achieve that. I agree that transformers are not straightforward to get right - I'm working on one myself these days. My problems seem (emphasis on seem at this stage) to be related to poor common mode rejection in the receiver, not a problem with the transformer itself. But its early days...

DO you know all the tricks to get these SPDIF transformers looking right on a TDR - if so please tell?

Nope, never played with such a beastie. I just get them looking OK on my scope - edges fairly sharp, no significant overshoot for example, no droop. What matters in the end is not so much how they look to the TDR but what the SPDIF receiver makes of them, which aspects result in extra jitter.

Except galvanic isolation which maybe worthwhile & in this instance perhaps more important as this is also USB

I think galvanic isolation is over-rated in this application. The problems seem to be interwinding capacitance (notice that Jocko's most unfavourite transformer manufacturer quotes 2pF interwinding capacitance - that's maybe for a reason). I haven't got anywhere near as low as that in my efforts. So in my view, isolation down to DC is fairly irrelevant - the transformer will pass common-mode RF noise through its interwinding capacitance and that's fairly certain to degrade the sound. YMMV.

jkeny

Banned
Oh, oh, here we go again - just let's not get into this argument about SPDIF transformers, etc. - you've stated what your preferences are.

abraxalito

Member
Oh, oh, here we go again - just let's not get into this argument about SPDIF transformers, etc. - you've stated what your preferences are.

I'm not aware of getting into a particular argument about SPDIF transformers and such. We're both interested in the same thing - getting good pulse fidelity and low interference with SPDIF.

Even if John's not interested, here are some suggestions for people who would like to attempt gilding the lily with SPDIF. I've gleaned many of these ideas from another place, so no claims to originality

Firstly using the DIT4192 to drive a cable isn't going to give ultimate performance in my estimation. That's because in the datasheet TI doesn't mention things that matter in RF line drivers like output impedance and rise times. So chances are, they've not thought about them. Secondly since the output drivers and logic share a common supply within the chip there's going to be noise on the supply which also means some jitter is inevitable.

The first step then is to reclock the DIT4192's output with a pico flip-flop powered from its own clean supply. I suggest looking at TI's 74AUC1G80 for this function. I've not looked closely at the DIT4192's datasheet to see which polarity of the master clock its output changes on, so this might need to be done by inspection - we don't want metastability problems in the flip-flop. Level shifters will also be needed (suitably chosen resistive dividers will suffice) between the clock and data signals and the flip-flop's inputs. The flip-flop's power supply voltage needs to be from 1-2.5V.

The end of the transmit chain is preferably a video opamp as this will have a well defined output impedance at all times, including the switching transitions. Between the flip-flop's output and the opamp sits a passive RC filter with a -3dB point somewhere between 50 - 100MHz which hopefully limits the rise time to 3-7nS or thereabouts. If you're going to run at 192kHz the 100MHz figure might be too low though. I'd go for 50MHz for up to 44k1 and 100MHz for 44k1 up to 96k.The video opamp needs to be unity gain stable, at least 100MHz UGBW and have a slew rate comfortably in excess of 330V/uS so I suggest looking at OPA890 and LM6171. The opamp's input filter is arranged to create a nice bandlimited pulse waveform of 1V peak which the opamp then sends via a series 75R termination into the cable. With a 75R termination there'll be a 500mV signal at the receiver.

That to me seems to be the best way to get the lowest possible jitter and noise on an SPDIF output. Anyone here see ways to improve on it? Note that there's no isolation transformer - isolation to be done at the input if required.

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jkeny

Banned
I'm not aware of getting into a particular argument about SPDIF transformers and such. We're both interested in the same thing - getting good pulse fidelity and low interference with SPDIF.
No, we didn't get into any dust-ups on SPDIF transformers - I just didn't want to go there - sorry if this came across as reading otherwise

Even if John's not interested, here are some suggestions for people who would like to attempt gilding the lily with SPDIF. I've gleaned many of these ideas from another place, so no claims to originality
I am interested & thank you for your posts

Firstly using the DIT4192 to drive a cable isn't going to give ultimate performance in my estimation. That's because in the datasheet TI doesn't mention things that matter in RF line drivers like output impedance and rise times. So chances are, they've not thought about them. Secondly since the output drivers and logic share a common supply within the chip there's going to be noise on the supply which also means some jitter is inevitable.
Perhaps, but I think that they do specify all the timings needed. Already calculated a rough output impedance but measurement is needed. You jogged my memory that the chip actually has a different supply Vcio for it's digital I/O section - so self-noise can be significantly reduced.

The first step then is to reclock the DIT4192's output with a pico flip-flop powered from its own clean supply. I suggest looking at TI's 74AUC1G80 for this function. I've not looked closely at the DIT4192's datasheet to see which polarity of the master clock its output changes on, so this might need to be done by inspection - we don't want metastability problems in the flip-flop. Level shifters will also be needed (suitably chosen resistive dividers will suffice) between the clock and data signals and the flip-flop's inputs. The flip-flop's power supply voltage needs to be from 1-2.5V.

The end of the transmit chain is preferably a video opamp as this will have a well defined output impedance at all times, including the switching transitions. Between the flip-flop's output and the opamp sits a passive RC filter with a -3dB point somewhere between 50 - 100MHz which hopefully limits the rise time to 3-7nS or thereabouts. If you're going to run at 192kHz the 100MHz figure might be too low though. I'd go for 50MHz for up to 44k1 and 100MHz for 44k1 up to 96k.The video opamp needs to be unity gain stable, at least 100MHz UGBW and have a slew rate comfortably in excess of 330V/uS so I suggest looking at OPA890 and LM6171. The opamp's input filter is arranged to create a nice bandlimited pulse waveform of 1V peak which the opamp then sends via a series 75R termination into the cable. With a 75R termination there'll be a 500mV signal at the receiver.

That to me seems to be the best way to get the lowest possible jitter and noise on an SPDIF output. Anyone here see ways to improve on it? Note that there's no isolation transformer - isolation to be done at the input if required.

Thanks for this

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abraxalito

Member
Perhaps, but I think that they do specify all the timings needed.

I missed the rise times for the transmit outputs then - what page are they on?

Already calculated a rough output impedance but measurement is needed.

I looked at the output stiffness (typical drop versus current) and guessed around 13ohms. But the worst case was more than double this. That gives the static output impedance but I'm betting it won't be maintained during transitions. The pico gate I mentioned though does have attention to such details so could be used as a driver all by itself.

You jogged my memory that the chip actually has a different supply Vcio for it's digital I/O section - so self-noise can be significantly reduced.

Ah thanks, I'd missed out on that point. Back to the datasheet....

jkeny

Banned
I missed the rise times for the transmit outputs then - what page are they on?
From page 7 can they not be calculated?

I looked at the output stiffness (typical drop versus current) and guessed around 13ohms. But the worst case was more than double this. That gives the static output impedance but I'm betting it won't be maintained during transitions. The pico gate I mentioned though does have attention to such details so could be used as a driver all by itself.
Yes, the pico gates could well be a better driver, I guess but I wonder how far the 4192 can get you?

Ah thanks, I'd missed out on that point. Back to the datasheet....

abraxalito

Member
From page 7 can they not be calculated?

My datasheet has page 7 talking about the audio serial input port. Are we looking at the same one? - mine's SBOS229B revised June 2003

Yes, the pico gates could well be a better driver, I guess but I wonder how far the 4192 can get you?

It will depend on all kinds of other factors in the system beyond the chip itself. But I'd really not expect what's essentially a logic chip to do equally well as an RF line driver. I note that the power supply figures quoted for the IO supply don't include driving the output into a real load even though they do give a recommended solution for that. Doesn't instill much confidence in that aspect for me.

jkeny

Banned
My datasheet has page 7 talking about the audio serial input port. Are we looking at the same one? - mine's SBOS229B revised June 2003

Joseph K & Fmak have measured the output stage of a Hiface which uses this device & found very fast rise times with some leading edge overshoot which may be the device or maybe the output stage? But anyway, it has a very fast rise time.

It will depend on all kinds of other factors in the system beyond the chip itself. But I'd really not expect what's essentially a logic chip to do equally well as an RF line driver. I note that the power supply figures quoted for the IO supply don't include driving the output into a real load even though they do give a recommended solution for that. Doesn't instill much confidence in that aspect for me.
I don't think this is essentially a logic device - it's TI's digital transmitter for the Pro Audio market with these integral output line drivers capable of outputting AES signal levels which is far more robust a signal than SPDIF!

abraxalito

Member
Joseph K & Fmak have measured the output stage of a Hiface which uses this device & found very fast rise times with some leading edge overshoot which may be the device or maybe the output stage? But anyway, it has a very fast rise time.

So you're not going to explain how you got the rise times from page 7 of the datasheet? I was hoping to learn something new there!

Fast rise time is what I'd expect from a logic chip. If you take on board the remarks of the RF gurus on diyhifi you'll realise that fast rise times are the problem (pace Steve Nugent who seems to think they're the solution) - they make it extremely hard to get an accurate termination of the cable. That's because the faster the rise time, the wider the bandwidth. Its rather odd they'd design a chip deliberately with fast rise times seeing as an SPDIF (and an AES/EBU for that matter) signal doesn't need very fast rise times - 7nS does perfectly well (may even be overkill) and makes the termination job so much easier.

I don't think this is essentially a logic device - it's TI's digital transmitter for the Pro Audio market with these integral output line drivers capable of outputting AES signal levels which is far more robust a signal than SPDIF!

Not the first time our opinions have diverged and almost certainly won't be the last. I realise the chip is capable of outputting AES/EBU signal levels - is that a badge of honour in your estimation?

jkeny

Banned
So you're not going to explain how you got the rise times from page 7 of the datasheet? I was hoping to learn something new there!

Fast rise time is what I'd expect from a logic chip. If you take on board the remarks of the RF gurus on diyhifi you'll realise that fast rise times are the problem (pace Steve Nugent who seems to think they're the solution) - they make it extremely hard to get an accurate termination of the cable. That's because the faster the rise time, the wider the bandwidth. Its rather odd they'd design a chip deliberately with fast rise times seeing as an SPDIF (and an AES/EBU for that matter) signal doesn't need very fast rise times - 7nS does perfectly well (may even be overkill) and makes the termination job so much easier.

Not the first time our opinions have diverged and almost certainly won't be the last. I realise the chip is capable of outputting AES/EBU signal levels - is that a badge of honour in your estimation?
Ok, let's not get contentious - You asked about rise times - I answered - I agree what you want is a rise time just fast enough but no faster so as to cut down on reflection issues.

My point is that the line drivers are capable of driving AES so not a wimpy output stage in answer to your "essentially a logic chip"

Let's not start a war! I have my opinion which differs from yours, that's OK

abraxalito

Member

Indeed I did. And you said 'can they not be calculated from page 7?' but decided not to explain how. So were you mistaken in that?

I agree what you want is a rise time just fast enough but no faster so as to cut down on reflection issues.

OK so we've reached common ground. So you still want to use a fast rise time output and deal with the reflection issues by some other means?

My point is that the line drivers are capable of driving AES so not a wimpy output stage in answer to your "essentially a logic chip"

Ah, I think I begin to see your error - you thought my 'essentially a logic chip' was a kind of put-down so you sprang to the device's defense. Touching but misplaced - it was just a classification, not pejorative. Logic chips can have meaty drivers, they're just not the same as RF line drivers.

Let's not start a war!

Don't mention the war! You've now mentioned it once, but perhaps you've got away with it.

I have my opinion which differs from yours, that's OK

Never suggested otherwise