Anti click-pop turn on/off for ir2110
I made d class amplifier with IR2110 drivers.....SHD pin of drivers works fine for on/off ....kind of mute....but there is click-pop sound on turn on.Some other solution would be very apreciated....and thank you all in advance.
I made d class amplifier with IR2110 drivers.....SHD pin of drivers works fine for on/off ....kind of mute....but there is click-pop sound on turn on.Some other solution would be very apreciated....and thank you all in advance.
Last edited:
The IR211x chips do not turn on immediately when SD pin transitions from high to low, turn on happens afterwards, on first HIN or LIN transition from low to high. In practice this can result in arbitrarily delayed turn on, or a click-pop as you describe. Optimum solution is going to depend on the rest of the circuit. Three ideas: using SD signal to pull HIN and LIN down as long as SD is high, using a LF signal injected into the input of the amplifier to force comparator toggling, and proper clamping of integrator.
Thank you Eva.I know all about IR211x chips.I know how its logic is working and i have pwm present when i am doing on off.I am using BD modulation and i have almost 100% phase match and very good amplifier design.Phase match i have is 99,99%.....and maybe 0-1mV DC on output without any input.My thinking was that becouse of perfect phase match i will have zero click pop on output.....but thats not the case.Idea about manipulating LIN and HIN at same time when SD is manipulated is good one.I had some thoughts about that but didnt try yet.Click pop is sometimes loud sometimes very quiet....I will try HIN LIN involving...if someone has some other idea i am open to hear.As few other people here i am developing my own D class concept (last few years) and all this help matters to me very much.
Last edited:
Do you have a precharge path for the floating high side driver section?
If not such chips can show output patterns which randomly deviate vs the input after enabling again.
The IR2110/IR2113 data sheet does not highlight a max d(VB-VS)/dt for charging the boot strap supply - but I already had devices of another brand (which is now the same brand 🙂 ) that started up with overlapping gate drive outputs simply because I trusted to use the first low side on signal for fast charging up of the floating boot strap supply...
...means if you have it not precharged, and charge it rapidly with the first pulse of the low side, then you might get a random behavior. Can do any noise, in worst case even cause a defect.
On the other hand if you have not precharged it but limit d(VB-VS)/dt i.e. with a resistor in series to the bootstrap diode, then VB-VS might grow too slowly and cause missing high side pulses. Plop, because output is more pulled down than up until VB-VS is sufficiently charged.
For this reason I am usually putting a precharge resistor from positive rail to VB and a 15V zener clamp between VB and VS.
Thank you ChocoHolic.I dont have charge limit resistor for high side - in serial with boot diode (thought that i dont need it becouse amp works good without it).....but it looks like that i have to try that solution too.I have solution number two where i can supply independantly voltage for high side (permanently) if that can solve pop also thats great (this is third possible solution 🙂 ).That can give infinite 100% duty cycle capability on output which i dont like but its ok ... i can live with that.Also precharge from plus rail is good idea....drawback is that i must use zener diode.I will try this as last step if all other options dont work 🙂 .
...last but not least there could be the reason in the modulator or gain stage.
I.e.:If you have an integrating gain stage without signal limitation (sometimes also named anti saturation) then your integrating gain will run to its max or min limit when the power stage is disabled, because disabling the power stage opens the feedback loop. After enabling the power stage it needs pretty long for the integrator to creep back to the required signal level.
Usually a limitation of the integrator output to a level slightly above the levels which are needed during normal operation does the trick.
This also is very helpful to improve clipping behavior.
The most simple clamp can be two antiserial zeners from the output of the integrating gain to GND.
A nicer (but in the end not necessarilly better, just ensuring that the current limiter of the OP remains an unemployed guy...) antisaturation limiter is shown the Kemp design on page 22-23.
https://scholar.sun.ac.za/handle/10019.1/20084
Don't put two antiserial zeners in the feedback loop of the OP amp, because there they would noticeably worsen distortion.
I.e.:If you have an integrating gain stage without signal limitation (sometimes also named anti saturation) then your integrating gain will run to its max or min limit when the power stage is disabled, because disabling the power stage opens the feedback loop. After enabling the power stage it needs pretty long for the integrator to creep back to the required signal level.
Usually a limitation of the integrator output to a level slightly above the levels which are needed during normal operation does the trick.
This also is very helpful to improve clipping behavior.
The most simple clamp can be two antiserial zeners from the output of the integrating gain to GND.
A nicer (but in the end not necessarilly better, just ensuring that the current limiter of the OP remains an unemployed guy...) antisaturation limiter is shown the Kemp design on page 22-23.
https://scholar.sun.ac.za/handle/10019.1/20084
Don't put two antiserial zeners in the feedback loop of the OP amp, because there they would noticeably worsen distortion.
And you are right again.Thx.This is not the case becouse i have antisat circuitry done already.One other way to influence pop is also to reduce boot capacitance for high side ...pop in that case will be super short....thus with very low effective value to produce sound.Thank you for paper about D class.I have it for few years already,but its a good point in this discussion.Pop in my case is when complete pwm is present all the time....no matter is my out on or off 🙂
Last edited:
Depending on the integrator and clamp topology used, and its time constants, there may be some advantage (the difference between small pop or no pop) by keeping the integrator reset just until the instant before the gate driver IC is activated. Thanks for the paper, I hadn't seen that one yet, I went a somewhat different design route.
Theoretically this would be a further improvement, but usually there are also P and D portions. Even if the integrating portion is slightly out of the needed range the P and D portions will bring the output of the regulator immediately close to the required value - in my experience this was always sufficient to get no plop.
...not sure if I got your idea right:
Wouldn't ramping cause a noticeable time during which that it will be different from 50%? Furtheron 50% is not necessarily pop free. Depending on supply rails you might need values slightly different from 50%. Well, in BTL you just need identical duty cycle on both legs.
Time i had in mind is 0,5sec ..... no matter whats output modulation it can be ramped from zero duty cycle to that current value on turn on......So instead having instantly output in in this case you will have fast zero - current value transition.I just designed that circuitry and tomorow i will make board so we will see.Chocoholic turn on your Skype if you have some time.I tried to write to you on pm here but your inbox is overloaded.
- Status
- Not open for further replies.