Hi everyone,
I'm currently designing a new dac based on sm5847 + pcm1704 (can't find ad1862s).
I want to use a master clock at 256fs for sm5847 and use that clock to directly feed the bck of the dacs, since this is the bck that really matters on these.
The question is:
does anyone know the delay between XTI (256 fs masterclock) and the bcko produced by the sm5847 (same freq with x8 os) ??
I measured the sm5842 at around 28ns, but I think the sm5847 is more powerful, maybe more delay ?
thanks to all
I'll post the schematic when it'll be over
I'm currently designing a new dac based on sm5847 + pcm1704 (can't find ad1862s).
I want to use a master clock at 256fs for sm5847 and use that clock to directly feed the bck of the dacs, since this is the bck that really matters on these.
The question is:
does anyone know the delay between XTI (256 fs masterclock) and the bcko produced by the sm5847 (same freq with x8 os) ??
I measured the sm5842 at around 28ns, but I think the sm5847 is more powerful, maybe more delay ?
thanks to all
I'll post the schematic when it'll be over
Sorry, I missed that part in the datasheet.
It's not explicitely said but it should be in phase. For this point, it's better than the previous 5842.
It's not explicitely said but it should be in phase. For this point, it's better than the previous 5842.
for flshzug : I bought them from vcamerica.com (10)
I plan to resell some after the project is finished.
For the reclocking, I didn't try yet with the sm5842. I plan to do it before the project with the sm5847, as a prototype.
My problem is that I need a bit more logic cause my actual dac is 20bit, so I have to add a 12bit shift register and delay the sm5842 clock to be in sync with the dac one (delay around 28ns for my sm5842).
Temporary schematic:
here
I plan to resell some after the project is finished.
For the reclocking, I didn't try yet with the sm5842. I plan to do it before the project with the sm5847, as a prototype.
My problem is that I need a bit more logic cause my actual dac is 20bit, so I have to add a 12bit shift register and delay the sm5842 clock to be in sync with the dac one (delay around 28ns for my sm5842).
Temporary schematic:
here
I finished wiring the reclocking board for the SM5842.
It is now working !
Here is the schematic:
Reclocker
The 30ns delay is inserted before the flip flops to be in phase with the output clock from sm5842 (bcko). It won't be needed for sm5847 cause the clock is already in phase.
The data are then processing through a 12bit shift register (20 bit dac) or 8 bits (24 bits dac).
The dac clock is the XTI one (the GOOD one).
I had to add some delay to wcko line so the falling edge is synced with the clock one.
It is now working !
Here is the schematic:
Reclocker
The 30ns delay is inserted before the flip flops to be in phase with the output clock from sm5842 (bcko). It won't be needed for sm5847 cause the clock is already in phase.
The data are then processing through a 12bit shift register (20 bit dac) or 8 bits (24 bits dac).
The dac clock is the XTI one (the GOOD one).
I had to add some delay to wcko line so the falling edge is synced with the clock one.
bit clock is directly the master clock and so contain less jitter than the one generated by the digital filter.
That's not the case of pcm1704 and that's the one i'm going to use for my new dac.
That was just a prototype to check the principe is good.
That was just a prototype to check the principe is good.
The PCM1704 also has no master clock and supports stopped clock operation. That is why it will work with the PMD100.
it does support stop clock operation, that's not the problem.
The digital to analog conversion happens at the second rising edge of bck after wclk goes low. Since the bck is generated by the digital filter and full of jitter, I want to use a clean clock for the dac.
two solutions:
- reclock the existing bck with a good clock
- directly feed the dac from the masterclock in continuous clock mode.
I choose the second solution.
The digital to analog conversion happens at the second rising edge of bck after wclk goes low. Since the bck is generated by the digital filter and full of jitter, I want to use a clean clock for the dac.
two solutions:
- reclock the existing bck with a good clock
- directly feed the dac from the masterclock in continuous clock mode.
I choose the second solution.
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