Hi,
Firstly from where does jitter come? The I2S hardware in any DSP is (derived) divided by the main system crystal, while reading allo kali reclocker, they claim the source of jitter is system crystal. I beg to differ, the crystal clock is already divided to generate I2S which essentially means several crystal clock pulses (allegedly jittery) are consumed to produce a single I2S clock, the jitter is well absorbed by these several clocks, if I2S were to really be affected by the main crystal jitter then only the main clock's last pulse jitter will reflect in I2S which isn't really much. Is the entire Kali reclocker a gimmick?
Kali reclocker is paired with Piano DAC 2.1 which uses PCM5142 which has a better jitter control than HiFiberry DAC8x. Does it mean that the former is far superior due to its own jitter better control and the alleged improvement from kali reclocker?
Thanks and Regards,
WonderfulAudio
Firstly from where does jitter come? The I2S hardware in any DSP is (derived) divided by the main system crystal, while reading allo kali reclocker, they claim the source of jitter is system crystal. I beg to differ, the crystal clock is already divided to generate I2S which essentially means several crystal clock pulses (allegedly jittery) are consumed to produce a single I2S clock, the jitter is well absorbed by these several clocks, if I2S were to really be affected by the main crystal jitter then only the main clock's last pulse jitter will reflect in I2S which isn't really much. Is the entire Kali reclocker a gimmick?
Kali reclocker is paired with Piano DAC 2.1 which uses PCM5142 which has a better jitter control than HiFiberry DAC8x. Does it mean that the former is far superior due to its own jitter better control and the alleged improvement from kali reclocker?
Thanks and Regards,
WonderfulAudio
It comes from very basic physics. Its a type of noise, but noise in the durationi analog time intervals rather than noise in amplitude.
In some cases jitter originates in crystal oscillators used in DACs and or in ADCs. Jitter can then be made worse by various physical processes, such as passage of a clock signal through a dac.
Jitter is the time domain name for errors (noise) in the duration of time intervals (i.e. unwanted variations in time clock accuracy). Time jitter can also be described in the frequency domain where it is referred to as phase noise. Phase noise (PN) is distinguished from amplitude noise (AN). That is to say, they are two different and orthogonal types of noise.
Probably not. There are application notes on time jitter and its effects on dacs published by various companies and in some scientific papers. Analog Devices is one company that has published application notes on jitter and phase noise in digital audio clocks and the resulting effects on data conversion.
Far superior? Is a very low noise phono preamp "far superior" to a somewhat higher noise phono preamp? "Far superior" is a vague description, not a measurement of some difference in a type of noise.
@wonderfulaudio : I will not discuss jitter, but just for comparison:
The proposed chain:
player -> in-memory DMA buffer -> RPi I2S transmitter in master mode clocked by very jittery clock generated by fractional division from non-audio-frequency PLL'd clock -> long FIFO in the Kali reclocker adding variable latency (initially 0.7s specced by the vendor) and eventually unavoidable buffer issues -> I2S master (bitclock, frameclock) clocked by precise master clock chip in the Kali reclocker -> I2S slave in PCM5142 -> master clock generated by internal DAC PLL from I2S bitclock -> the actual DA conversion clocked by the PLL'd master clock
Vs. the IMO logical chain:
player -> in-memory DMA buffer -> RPi I2S transmitter in slave mode clocked by incoming bit/frameclocks -> I2S master in PCM5142, bit/frame clocks generated by PCM5142 itself from precise master clock chip -> the actual DA conversion clocked by the precise master clock
No need for any reclocker with dumb plain FIFO which will always over/underrun after some time and add a major latency. No need for jittery regeneration of the MCLK by the DAC. Plus there already is a MCLK in the reclocker, but the DACs do not use it because the RPi pinheader does not have a dedicated pin for MCLK and the reclocker could not be just inserted onto the pinheader between the DAC and RPi, damaging sales of the extra (IMO technically incorrect and unnecessary) board...
The proposed chain:
player -> in-memory DMA buffer -> RPi I2S transmitter in master mode clocked by very jittery clock generated by fractional division from non-audio-frequency PLL'd clock -> long FIFO in the Kali reclocker adding variable latency (initially 0.7s specced by the vendor) and eventually unavoidable buffer issues -> I2S master (bitclock, frameclock) clocked by precise master clock chip in the Kali reclocker -> I2S slave in PCM5142 -> master clock generated by internal DAC PLL from I2S bitclock -> the actual DA conversion clocked by the PLL'd master clock
Vs. the IMO logical chain:
player -> in-memory DMA buffer -> RPi I2S transmitter in slave mode clocked by incoming bit/frameclocks -> I2S master in PCM5142, bit/frame clocks generated by PCM5142 itself from precise master clock chip -> the actual DA conversion clocked by the precise master clock
No need for any reclocker with dumb plain FIFO which will always over/underrun after some time and add a major latency. No need for jittery regeneration of the MCLK by the DAC. Plus there already is a MCLK in the reclocker, but the DACs do not use it because the RPi pinheader does not have a dedicated pin for MCLK and the reclocker could not be just inserted onto the pinheader between the DAC and RPi, damaging sales of the extra (IMO technically incorrect and unnecessary) board...
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