I'm trying to hook up my amanero to the PCM1975 but I'm confused by the pinout in the datasheet.
I don't understand why SCK and BCK are seperate.
I also don't understand why it is telling me to use a 10 ohm resistor on MCLK when there is no MCLK pin.
The amanero pinout is Data, BCK, FSCLK, and MCLK.
I'm not sure what to do here.
I don't understand why SCK and BCK are seperate.
I also don't understand why it is telling me to use a 10 ohm resistor on MCLK when there is no MCLK pin.
The amanero pinout is Data, BCK, FSCLK, and MCLK.
I'm not sure what to do here.
That's an interesting, if confusing, layout diagram. Anyhow...
1. SCK = System Clock = MCLK = Master Clock.
2. BCK = Bit Clock = SCLK = Shift Clock = serial bit clock.
These are different designators for the same clock signals. Some DIR chips use the MCLK naming for the high rate clock signal. A bit sloppy, perhaps, for the PCM1795 data sheet to refer to both MCLK and SCK.
While I'm not familiar with the details of the Amanero USB module, I feel fairly sure that the following definitions apply:
DATA = self explanatory
BCK = serial bit clock
FSCLK = frame sync. clock = LRCK = left right clock
MCLK = master clock = SCK = system clock
I do find it interesting that the use of a top layer ground pour around the DAC is recommended. I hadn't noticed that before now.
1. SCK = System Clock = MCLK = Master Clock.
2. BCK = Bit Clock = SCLK = Shift Clock = serial bit clock.
These are different designators for the same clock signals. Some DIR chips use the MCLK naming for the high rate clock signal. A bit sloppy, perhaps, for the PCM1795 data sheet to refer to both MCLK and SCK.
While I'm not familiar with the details of the Amanero USB module, I feel fairly sure that the following definitions apply:
DATA = self explanatory
BCK = serial bit clock
FSCLK = frame sync. clock = LRCK = left right clock
MCLK = master clock = SCK = system clock
I do find it interesting that the use of a top layer ground pour around the DAC is recommended. I hadn't noticed that before now.
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So, if SCK is MCLK, does it benefit from a quality external oscillator in the same way the ESS dac does? it's not mentioned in the datasheet.
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For optimal performance, it is important to use a clock source with low phase jitter and noise. The Texas Instruments PLL1700 family of multiclock generators is an excellent choice to provide the PCM1795 system clock
PCM1795 datsheet page 21
PCM1795 datsheet page 21
Oh so I'll need to use the amanero in slave mode then, assuming I care enough to make an ultra HQ XO for a $5 dac chip.
How does the PCM1795 compare to the ESS chips anyway?
How does the PCM1795 compare to the ESS chips anyway?
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