😕Is it possible to connect the output of buffalo 2 (gnd and +) to the to the unbalanced input of the passlabs B1 buffer ?
Regards,
Berry
Regards,
Berry
Thanx for the answer,
They say what is in the text below, but the input inpedance of the b1 is also very low, or not ?
"The Buffalo II does not include an output stage but is designed to mate with the IVY III current to voltage
stage. It is not recommended to use the Buffalo II output directly, but it is possible. The output can be used
as a voltage source into a high impedance but THD+N will suffer. THD+N as a voltage source is about -
108db whereas when used with a very low input impedance current to voltage stage such as the IVY-III it
can achieve -120db THD+N in mono mode.
Each analog output at 0DBFS is equivalent to a voltage of approximately 92.4% of AVCC in series with
195. So given 3.3VDC AVCC it will be about 3.05Vpp across 195. The output will be DC biased at
AVCC/2. This works out to about 16ma peak to peak at each output. The amount of bias current will depend
of the voltage of the virtual ground."
They say what is in the text below, but the input inpedance of the b1 is also very low, or not ?
"The Buffalo II does not include an output stage but is designed to mate with the IVY III current to voltage
stage. It is not recommended to use the Buffalo II output directly, but it is possible. The output can be used
as a voltage source into a high impedance but THD+N will suffer. THD+N as a voltage source is about -
108db whereas when used with a very low input impedance current to voltage stage such as the IVY-III it
can achieve -120db THD+N in mono mode.
Each analog output at 0DBFS is equivalent to a voltage of approximately 92.4% of AVCC in series with
195. So given 3.3VDC AVCC it will be about 3.05Vpp across 195. The output will be DC biased at
AVCC/2. This works out to about 16ma peak to peak at each output. The amount of bias current will depend
of the voltage of the virtual ground."
Apparently it is optimal into a virtual ground. Instead of a
buffer, I suggest you use a fet operated Common Gate, the
example being the I/V converter in the PL D1.
😎
buffer, I suggest you use a fet operated Common Gate, the
example being the I/V converter in the PL D1.
😎
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