Hey guys,
Just built my first ever amp, a minimalist FET source follower (a Szekeres headphone amp, but using the tiny 2N7000).
I've wrapped my head around LTSpice enough to be able to plot IV curves and load lines, and now I'm trying to develop a better intuition about what kind of load line results in the lowest distortion.
Most of the load line tutorials I have come across all assume that you want the maximum amount of operating area possible, so they all draw a load line which hangs just below the curve of maximum allowable heat, and then bias it right in the middle.
Here's what that would look like for me. These are the IV curves for a 2N7000, with a 650mW heat limit curve, and a 18V / 150 Ohm load line. The two cursors indicate a +/-100mV area of operation.
However, I'm a bit of an unusual case, because I need barely any voltage swing (even just 50mV RMS is already pretty loud with the Phillips SHE3580 headphones I'm driving). This means I can basically pick any area of operation I want along the IV curves.
So the question is, which area would yield the least distortion? And the follow up questions would be "why?". Is it the slope of the load line? The amount of quiescent current through the FET? And which should you favor, given the choice?
One option would be to use a low bias voltage, with a large amount of quiescent current through the FET (e.g. operate in the upper left area):
The polar opposite idea would be to bias it with high voltage, with a small amount of quiescent current, but use a very small resistor so that the slope of the load line is very high (which would cause a much higher current swing):
Yet another idea would be to go for the lowest slope possible on the load line. We can do that by using a large resistor:
So my question is, which yields the best distortion figures? Upper left area? Lower right area? Large load line slope? Small load line slope? Etc?
Just built my first ever amp, a minimalist FET source follower (a Szekeres headphone amp, but using the tiny 2N7000).
I've wrapped my head around LTSpice enough to be able to plot IV curves and load lines, and now I'm trying to develop a better intuition about what kind of load line results in the lowest distortion.
Most of the load line tutorials I have come across all assume that you want the maximum amount of operating area possible, so they all draw a load line which hangs just below the curve of maximum allowable heat, and then bias it right in the middle.
Here's what that would look like for me. These are the IV curves for a 2N7000, with a 650mW heat limit curve, and a 18V / 150 Ohm load line. The two cursors indicate a +/-100mV area of operation.
However, I'm a bit of an unusual case, because I need barely any voltage swing (even just 50mV RMS is already pretty loud with the Phillips SHE3580 headphones I'm driving). This means I can basically pick any area of operation I want along the IV curves.
So the question is, which area would yield the least distortion? And the follow up questions would be "why?". Is it the slope of the load line? The amount of quiescent current through the FET? And which should you favor, given the choice?
One option would be to use a low bias voltage, with a large amount of quiescent current through the FET (e.g. operate in the upper left area):
The polar opposite idea would be to bias it with high voltage, with a small amount of quiescent current, but use a very small resistor so that the slope of the load line is very high (which would cause a much higher current swing):
Yet another idea would be to go for the lowest slope possible on the load line. We can do that by using a large resistor:
So my question is, which yields the best distortion figures? Upper left area? Lower right area? Large load line slope? Small load line slope? Etc?
Whatever gives highest Id. What is why simple source / emitter followers tend to perform best when the output is as close to the positive rail as possible without running into clipping. A kingdom for a current source.
Note that effective load impedance (at AC) = Rs || Rload. That's about the same for all cases because Rload = 16 ohms and thus a fair bit smaller than Rs. Hence, highest Id wins. Results may be different when feedback capacitance dominates distortion.
650 mW on a poor little TO-92? Yikes. You know what thermal resistance is on these? (180 K/W or so.)
Your terminology is confusing. What you called Vd is more like Vs, right? And then it should be (18-Vs) for the power limit.
Note that effective load impedance (at AC) = Rs || Rload. That's about the same for all cases because Rload = 16 ohms and thus a fair bit smaller than Rs. Hence, highest Id wins. Results may be different when feedback capacitance dominates distortion.
650 mW on a poor little TO-92? Yikes. You know what thermal resistance is on these? (180 K/W or so.)
Your terminology is confusing. What you called Vd is more like Vs, right? And then it should be (18-Vs) for the power limit.
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