Multiformat SPDIF receiver

[quantran]

Hi all

I am designing a SPDIF receiver using CS8414 chip. This includes asynchronous reclocking and will be compatible with I2S, 16 bit, 18 bit, 20 bit and 24 bit right justified formats.

Attached is the schematic. It would be appreciate if you can give some comments on this design. Does the logic look OK?

One thing that I am not sure is the current consumption of the 74HC74 and 74HC164 chips. Some datasheets say +/-50mA through Vcc and GND pins. This sounds strange to me. Could some one explain this?

Cheers

 

[quantran]

No one has comments?

I plan to use this receiver for PCM63 NOS DAC. It seems that there are very few NOS PCM63 DAC around. The receiver can also be used with PCM56, PCM1704, AD1862, AD1865, TDA1541, TDA1543.

CS8414 operates in mode 11 with Asynchronous BCK input.

One 74hc74 is used to derive BCK

2x 74hc164 to shift data for desired output format

Second 74hc74 is used for reclocking and inverting Fsync for Right channel

 

[hagtech]

Power dissipation of cmos logic is mainly a function of switching rate, capacitance, and supply voltage. Do not confuse actual operating conditions with absolute maximum ratings. Driving a capacitive load (like a cmos input) requires power:

P = C * f * V * V;

For the schematics:

1) Do not use a film or low ESR cap at the output of that regulator. It can cause instability.

2) I believe the RXN input needs to be driven. Maybe this works ok, I'll have to think about it.

3) How do you synchronize clocks? Or is this ASRC where some samples are either skipped or repeated every once in awhile?

4) Why separate regulators for each digital chip? They have to talk to each other directly, so may as well be on same supply. You can use passive components to decouple. Nothing like a ferrite bead between parts.

jh

 

[quantran]

Hi hagtech

Thanks for your comments. I am reconsidering the power supply. I have some REG104-5 regulators. Do you think use one of these to supply all digital chips including the crystal oscillator would be a better solution?

Regarding you second question, I think some people have used a pulse transformer this way with cs8414 (or 8412).

For your 3rd question, with CS8414 running in mode 11, if fed with 2.8224Mhz BCK, the receiver will use that clock signal to decode SPDIF and provide DATA and FSYNC output. I believe that CS8414 should take care of the synchronisation of BCK input and the outputs. Please correct me if I am wrong.

DATA and FSYNC output from CS8414 would then be reclocked with 74hc74. Clock signal feeding this 74hc74 is the BCK clock source that feeds CS8414.

Any other comments are welcome.

Cheers