I was playing around in ngspice and was wondering why a particular design decision is typically made.
When output stages are designed for output power greater than 200 W, typically for Darlington stages, even triple stages, higher VAS currents are used on the order of 10 mA. This requires the use of transistors like 3503/1381 pair for the VAS to handle the power dissipation of a rail voltage greater than 50 V and 10 mA (or about 500 mW to 1000 mW static dissipation). However, why is 10 mA needed for a triple Darlington configuration? In the designs like below, 2 mA seems to be sufficient for a triple Darlington, which for 70 V and 2 mA would be 140 mW of static dissipation, well within the range of a TO-92 device such as 2N5551/2N5401.
Is this a matter of just wanting the extra current to make sure there is no VAS distortion? Or is there some other reason for it? It seems to work (at least in simulation) with less VAS current and a triple as the higher current gain in the triple makes up for the lower VAS current.
I am interested in this question because I am curious about how to pare a design down to the barebones to get good performance but not require anything too fancy.
When output stages are designed for output power greater than 200 W, typically for Darlington stages, even triple stages, higher VAS currents are used on the order of 10 mA. This requires the use of transistors like 3503/1381 pair for the VAS to handle the power dissipation of a rail voltage greater than 50 V and 10 mA (or about 500 mW to 1000 mW static dissipation). However, why is 10 mA needed for a triple Darlington configuration? In the designs like below, 2 mA seems to be sufficient for a triple Darlington, which for 70 V and 2 mA would be 140 mW of static dissipation, well within the range of a TO-92 device such as 2N5551/2N5401.
Is this a matter of just wanting the extra current to make sure there is no VAS distortion? Or is there some other reason for it? It seems to work (at least in simulation) with less VAS current and a triple as the higher current gain in the triple makes up for the lower VAS current.
I am interested in this question because I am curious about how to pare a design down to the barebones to get good performance but not require anything too fancy.
The VAS biased 4mA, in my power amplifier. Output is triple darlington using KSC3503/KSA1381+2SC4883/2SA1859+NJW3281/NJW1302. Comfortably drives my speakers which have 2,7ohms minimum impedance.
The Miller capacitance also robs current which could be used to drive the output stage (at high frequency). If the VAS is biased lower than the stage that drives it, the VAS instead of the input pair could actually limit the slew rate. Take two milliamperes away from 10, and you’ve still got 8. Take two away from two, and it leaves you with nothing. 6 mA in the VAS is often a good compromise, if you don’t need to drive a heavy load. If you want to use small signal TO92’s in the VAS at higher voltages, just parallel a couple.
What if the VAS is being driven by an emitter follower stage? That helps provide current to overcome the Miller effect in the common emitter stage.
The cap must also charge through the VAS itself. If you have a two milliamp current source n the collector, that’s all you get to charge the cap AND drive the output triple. Doesn’t matter if you have 20 available for driving it on the base side - you won’t use it all.
