You can just cut the PCB around the source terminal of the fet. Then solder to that.
Of course distortion will increase with load, if you want to drive 600 ohm loads you can just put another stage onto this one. It's already loaded with 68k so if you add a stage with like >100k impedance it wont drastically increase the THD.
This is just to interface with the mic capsule and get a more robust source output. Since <<5pF input capacitance is not that trivial to achieve and still have descent performance.
Here the fet is bootstrapped so the miller capacitance is minimized. And loaded with a CC source to reduce the 2nd harmonic.
Of course distortion will increase with load, if you want to drive 600 ohm loads you can just put another stage onto this one. It's already loaded with 68k so if you add a stage with like >100k impedance it wont drastically increase the THD.
This is just to interface with the mic capsule and get a more robust source output. Since <<5pF input capacitance is not that trivial to achieve and still have descent performance.
Here the fet is bootstrapped so the miller capacitance is minimized. And loaded with a CC source to reduce the 2nd harmonic.
Last edited:
I improved the circuit by buffering the source of the fet. But now I have a problem where the signal from the "constant" current source gets fed back into the gate since it's internally biased to the source. So then because of the phase lag on the CC source it creates a resonant peak.
THD is now at the measurement floor @ 5ns for 10ms. Previous results had 10ns simulations so they were too at the measurement floor ~50ppm THD
Which about that... Is there a way to get faster THD simulations in LTSpice or do I just have to run it for an hour?
THD is now at the measurement floor @ 5ns for 10ms. Previous results had 10ns simulations so they were too at the measurement floor ~50ppm THD
Which about that... Is there a way to get faster THD simulations in LTSpice or do I just have to run it for an hour?
I think the bias point is quite unpredictable. According to the datasheet at https://www.linearsystems.com/jfet-amplifiers-duals/2n/ls5905-series the IDSS of 1/2 LS5909 can be anything between 60 uA and 1 mA, while the pinch-off voltage can be anything between -0.6 V and -4.5 V. If you have a 60 uA JFET with -0.6 V pinch-off voltage, Q26 won't turn on.
If you have a 1 mA JFET with -4.5 V pinch-off voltage, Q26 would get more than half a milliamp of base current if the JFET were in saturation. In fact, the DC output voltage will then increase until Q23 saturates and the voltage across the JFET drops so far that its drain current drops to whatever Q26 needs. The JFET will be deep in the triode region and won't work as a decent source follower anymore; the gain will collapse and the equivalent input noise will go through the roof.
If you would connect the bottom side of the 1 Gohm resistor to a suitable bias voltage, give the JFET its own current source (not a gyrator, but a real current source) with a value just below 60 uA and give the emitter follower its own current source, you would have a far more predictable bias point. There would be about 4 V of variation on the output voltage depending on the precise JFET parameters, but the currents would be predictable and you could predictably keep the bipolar transistors out of saturation and the JFET out of the triode region. Actually you also have to increase the voltage across R47 to about 6 V to keep the JFET out of the triode region if it has a -4.5 V pinch-off.
If that's not possible because the JFET and resistor are actually built into the capsule, you could just take the circuit of post #1 with an emitter follower biased with a current source (no gyrator) after it.
If you have a 1 mA JFET with -4.5 V pinch-off voltage, Q26 would get more than half a milliamp of base current if the JFET were in saturation. In fact, the DC output voltage will then increase until Q23 saturates and the voltage across the JFET drops so far that its drain current drops to whatever Q26 needs. The JFET will be deep in the triode region and won't work as a decent source follower anymore; the gain will collapse and the equivalent input noise will go through the roof.
If you would connect the bottom side of the 1 Gohm resistor to a suitable bias voltage, give the JFET its own current source (not a gyrator, but a real current source) with a value just below 60 uA and give the emitter follower its own current source, you would have a far more predictable bias point. There would be about 4 V of variation on the output voltage depending on the precise JFET parameters, but the currents would be predictable and you could predictably keep the bipolar transistors out of saturation and the JFET out of the triode region. Actually you also have to increase the voltage across R47 to about 6 V to keep the JFET out of the triode region if it has a -4.5 V pinch-off.
If that's not possible because the JFET and resistor are actually built into the capsule, you could just take the circuit of post #1 with an emitter follower biased with a current source (no gyrator) after it.
Last edited: