Hello!
Here is just another variant of Bob Cordell's fantastic sinewave generator (as part of his THD analyzer). It uses 4 or 5 (without or with frequency fine tuning) identical relay boards as replacement for the switch. And I tried to change the amplitude measurement by using two sample & hold circuits. Dimensions of the generator without power supply and µC are 100x65x40mm³.
Unfortunately, the first attempt only gives around -100dB THD (10Hz to 100kHz, at up to 250kHz measurement bandwidth). Beside the multiplier it seems that the S&H degrades the performance; there is a 5mV step at the output of sample & hold no. 2 at constant input voltage.
I would be very thankful for comments about improving the performance. Details can be found in the attachment and my website (sinusgenerator).
Best regards,
Michael
Here is just another variant of Bob Cordell's fantastic sinewave generator (as part of his THD analyzer). It uses 4 or 5 (without or with frequency fine tuning) identical relay boards as replacement for the switch. And I tried to change the amplitude measurement by using two sample & hold circuits. Dimensions of the generator without power supply and µC are 100x65x40mm³.
Unfortunately, the first attempt only gives around -100dB THD (10Hz to 100kHz, at up to 250kHz measurement bandwidth). Beside the multiplier it seems that the S&H degrades the performance; there is a 5mV step at the output of sample & hold no. 2 at constant input voltage.
I would be very thankful for comments about improving the performance. Details can be found in the attachment and my website (sinusgenerator).
Best regards,
Michael
Thanks for all of your work!
It's good to see that design updated with modern devices. Those multi-pole rotary switches were a deterrent to DIY construction even when the project was published 35 years ago.
There are at least two (very) long threads on the forum where possible improvements (including sample-and-hold detectors) to this circuit have been discussed:
http://www.diyaudio.com/forums/equipment-tools/205304-low-distortion-audio-range-oscillator.html
http://www.diyaudio.com/forums/equipment-tools/231665-shibasoku-automatic-distortion-analyzer.html
Dale
It's good to see that design updated with modern devices. Those multi-pole rotary switches were a deterrent to DIY construction even when the project was published 35 years ago.
There are at least two (very) long threads on the forum where possible improvements (including sample-and-hold detectors) to this circuit have been discussed:
http://www.diyaudio.com/forums/equipment-tools/205304-low-distortion-audio-range-oscillator.html
http://www.diyaudio.com/forums/equipment-tools/231665-shibasoku-automatic-distortion-analyzer.html
Dale
I think that -100 dB THD is pretty good.
Possibly swapping the AD633 Multiplier channels over may lower distortion because according to the data sheet the Y channel has a lower non linearity than the X channel.
If the budget can stretch to it the Texas Instruments MPY634 claims that the typical Y channel linearity is better than the AD633. I used the MPY634.
If their is a problem with the Sample and Hold step it may be possible to reduce it. I used a 'discrete' sample and hold using an Analog Devices ADG1221 which has really low charge injection that caused no discernible step.
Possibly swapping the AD633 Multiplier channels over may lower distortion because according to the data sheet the Y channel has a lower non linearity than the X channel.
If the budget can stretch to it the Texas Instruments MPY634 claims that the typical Y channel linearity is better than the AD633. I used the MPY634.
If their is a problem with the Sample and Hold step it may be possible to reduce it. I used a 'discrete' sample and hold using an Analog Devices ADG1221 which has really low charge injection that caused no discernible step.
I presume you're mainly interested in improving THD/THD+N (there are more performance aspects, e.g. settling time and amplitude flatness)?
There are of course numerous possible distortion sources at the -100 dB level, and it's hard to guess which one dominates in your circuit. The main suspects at this level (amplifiers and passives should contribute much less distortion unless something is seriously wrong) are control voltage ripple, nonlinear feedthrough of the multiplier and layout effects.
Only a systematic approach that isolates every single potential distortion source will give you a good chance of success. If you suspect that control voltage ripple is the issue, you can e.g. double the value of R13 and see if distortion rises in proportion (this also increases the loop gain of the leveling loop--I don't think this affects operation of this design, but in case it does, try a smaller value for R13. Distortion should then drop). Or construct a simulation where the only non-ideality is the leveling loop ripple, and see if that matches your measurement result.
Samuel
PS: It looks like you're feeding the output directly to a coax cable; capacitive loading will likely cause U3 to oscillate. You should include a series resistor of ~50 Ohm.
There are of course numerous possible distortion sources at the -100 dB level, and it's hard to guess which one dominates in your circuit. The main suspects at this level (amplifiers and passives should contribute much less distortion unless something is seriously wrong) are control voltage ripple, nonlinear feedthrough of the multiplier and layout effects.
Only a systematic approach that isolates every single potential distortion source will give you a good chance of success. If you suspect that control voltage ripple is the issue, you can e.g. double the value of R13 and see if distortion rises in proportion (this also increases the loop gain of the leveling loop--I don't think this affects operation of this design, but in case it does, try a smaller value for R13. Distortion should then drop). Or construct a simulation where the only non-ideality is the leveling loop ripple, and see if that matches your measurement result.
Samuel
PS: It looks like you're feeding the output directly to a coax cable; capacitive loading will likely cause U3 to oscillate. You should include a series resistor of ~50 Ohm.
PChi, I didn't know the MPY634, thanks for the hint. Samuel, you are absolutely right, at first the potential distortion sources have to be isolated. I already tried to increase R8 which made distortion worse. 50 Ohms in series to U3's output is never a bad idea. (By the way, your design is really amazing; thanks for sharing your knowledge!)
Something different: did someone of you every try to use an ADC as S&H (for example the LTC2326 with separate convert pin), do the reference and servo stuff in a µC and control the multiplier by a DAC (or use a multiplying DAC)?
Something different: did someone of you every try to use an ADC as S&H (for example the LTC2326 with separate convert pin), do the reference and servo stuff in a µC and control the multiplier by a DAC (or use a multiplying DAC)?
Regarding multipliers: Note that the nonlinearity quoted in datasheets is of no (direct) relevance to this application. Once settled, the control voltage is nominal zero. Thus only the nonlinear feedtrough of the multiplier is relevant. Unfortunately, this figure is not usually specified, so must be measured. The total (linear + nonlinear) feedthrough as specified in the datasheets might be at least a basic indicator. I suspect that the AD734 has the lowest nonlinear feedthrough of any currently available IC multiplier, but its price tage has so far prevented me from actually verifying this assumption.
Of paramount importance is the optimization of the leveling loop gain and "authority" (control range) of the multiplier. I haven't looked at your circuit in that much detail, but as the AD633 probably has a different multiplier constant and control voltage range than the original JFET multiplier there might be room for significant enhancements without going for a more expensive multiplier.
Yes, member davada has implemented this approach and there is also a IEEE paper covering a (rather poor) implementation.
Samuel
Of paramount importance is the optimization of the leveling loop gain and "authority" (control range) of the multiplier. I haven't looked at your circuit in that much detail, but as the AD633 probably has a different multiplier constant and control voltage range than the original JFET multiplier there might be room for significant enhancements without going for a more expensive multiplier.
Yes, member davada has implemented this approach and there is also a IEEE paper covering a (rather poor) implementation.
Samuel
Thanks for all the hints thus far ...
I recently had time for some simulations of the S&H ripple contribution on the overall performance of the oscillator. Using an ideal behavioral multiplier the effect of 1mV ripple in the S&H increased 2nd harmonic by up to 20dB! I now added a portion of the 2nd S&H control signal to the input of the error amplifier to compensate the ripple. The THD of the oscillator is now -105dB to -110dB.
It would still be interesting to use ADC/DAC instead of the bare S&H: (beside being costly) the integrated S&Hs are not intended for using both sample and hold output. The AD783 data sheet says +/-5mV hold mode offset and up to 200mV sample mode offset. I simulated the influence of ADC/DAC quantization and compared it with an ideal S&H: 16bit made THD worse by 3dB only. Maybe the better and lower cost solution for a approx. -110dB oscillator? An experiment will show ...
I also tried to exchange X and Y inputs of the AD633 multiplier since PChi mentioned that nonlinearity is lower on Y than X input (+/-0.1% vs. +/-0.4%). Unfortunately, THD became worse by around 3dB. So, Samuel's theory seems to be right. I have to check this another time.
Michael
I recently had time for some simulations of the S&H ripple contribution on the overall performance of the oscillator. Using an ideal behavioral multiplier the effect of 1mV ripple in the S&H increased 2nd harmonic by up to 20dB! I now added a portion of the 2nd S&H control signal to the input of the error amplifier to compensate the ripple. The THD of the oscillator is now -105dB to -110dB.
It would still be interesting to use ADC/DAC instead of the bare S&H: (beside being costly) the integrated S&Hs are not intended for using both sample and hold output. The AD783 data sheet says +/-5mV hold mode offset and up to 200mV sample mode offset. I simulated the influence of ADC/DAC quantization and compared it with an ideal S&H: 16bit made THD worse by 3dB only. Maybe the better and lower cost solution for a approx. -110dB oscillator? An experiment will show ...
I also tried to exchange X and Y inputs of the AD633 multiplier since PChi mentioned that nonlinearity is lower on Y than X input (+/-0.1% vs. +/-0.4%). Unfortunately, THD became worse by around 3dB. So, Samuel's theory seems to be right. I have to check this another time.
Michael
Have you looked at the loop gain of your leveling loop? There's no point looking for any other solution before you've got this right.
www.eecg.toronto.edu/~pagiamt/kcsmith/vannerson-smith-low-distortion-oscillator.pdf is a good source on this topic.
Samuel
www.eecg.toronto.edu/~pagiamt/kcsmith/vannerson-smith-low-distortion-oscillator.pdf is a good source on this topic.
Samuel
- Status
- Not open for further replies.