J Fet selection

[hazard500]

I've designed a balanced j-fet phono stage, have all the devices and would appreciate some advice on which fets to use.

The amp will have 3 stages - first is an n j-fet (2SK369) with passive eq for 50Hz and 500Hz, which cascades into the second stage which will be a p j-fet (2SJ74) with passive eq for 2122Hz and 50kHz. The final stage will be another 2SK369 stage, with variable gain - this isolates eq from the outside world and eliminates need for a pre-amp. Think of it like an Allen Wright real-time pre-amp, done with fets instead of valves.

I've sorted and matched all my Fets, and my question is this - for the second stage, I have a collection of 50 2SJ74's (violet) and Idss for these range from 11.5mA to 19mA. I have got plenty enough pairs matched to 1% to make a long tail pair. The LTP will run total current of 20mA ie 10mA in each device. I assume that I should use the pair of fets with lowest Idss, as my reading of the data sheet is that, for a fixed drain current, the device with lowest Idss has the highest gain. Is my thinking sound? I've got plenty of pairs, with Idss of 12mA to Idss 18mA so any answer is good for me! Thanks for any useful advice.

 

[EUVL]

Something like this ?
http://www.diyaudio.com/forums/analogue-source/54658-all-jfet-open-loop-riaa-pre-amp.html

50x 2SJ74V's. What a luxury.

If the LTP total current is 20mA, and you expect to swing say 15mA through one of those legs (e.g. in a non-global-feedback circuit), then you should use Idss 15mA+ for the diff pair. This ensures that the JFET is never reversed biased (i.e. Vgs always positive for P-JFET).

The 15mA quoted above is an arbitrary figure as an example. Real value depends on your circuit.


Patrick

 

[hazard500]

Something like this ?
http://www.diyaudio.com/forums/analogue-source/54658-all-jfet-open-loop-riaa-pre-amp.html

50x 2SJ74V's. What a luxury.

If the LTP total current is 20mA, and you expect to swing say 15mA through one of those legs (e.g. in a non-global-feedback circuit), then you should use Idss 15mA+ for the diff pair. This ensures that the JFET is never reversed biased (i.e. Vgs always positive for P-JFET).

The 15mA quoted above is an arbitrary figure as an example. Real value depends on your circuit.


Patrick

Well yes very similar! There is after all nothing new under the sun. Main differences are
1. I'm using single not double fets - could give me a problem with offset but I've matched them so that Idss difference is less than 0.1mA.
2. I'm aiming to run a much higher tail current, such that fets are running close to Idss - 8mA per device for 369Bs, 10mA per device for 74Vs.
3. My power amp is balanced, so the 3rd stage will be another LTP that looks pretty much like first stage, rather than the single end push pull output here.
4. I'm gonna use a switched attenuator across the drains of the LTP - will provide gain adjustment (and fets like lower loads so should run it at lowest possible load IIRC). I use this arrangement in a strain gauge pre-amp I built up with 2SK369s, and it works a treat.
5. And therefore I'll have DC offset at the output, I'm gonna use a Lundahl 1527LX across drains of the output LTP.

So, I cribbed my design from Allen Wright (RIP). What is genesis of this?

Ive got 2 74s, Idss 15.09mA, 15.11mA - these should be close enough - thanks for the tip.

Paul