An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
Meet this DAC's audition
My girl friend is said . Like having exchanged the small plate . Sound ( my girl friend does not understand sound ) that it is very beautiful
xiaolong is my friend.we have worked on team on the other projects.
to Bernhard
he work for a UPS company, designer.
PCB only,he has been busy🙂
sch file available.
to Bernhard
he work for a UPS company, designer.
PCB only,he has been busy🙂
sch file available.
LOGIC
Hi,
Looking at the schematic, the 74HC02 is sending inverse signals of Sdata and Fsync to the right channel of AD1865 and normal ones to the left. I've seen it done in a double DAC setup with balanced output. But I don't quit understand what the data structure is in an un-balanced setup such as this one. Explanation in simple English is much appreciated.
Cheers,
K K
Hi,
Looking at the schematic, the 74HC02 is sending inverse signals of Sdata and Fsync to the right channel of AD1865 and normal ones to the left. I've seen it done in a double DAC setup with balanced output. But I don't quit understand what the data structure is in an un-balanced setup such as this one. Explanation in simple English is much appreciated.
Cheers,
K K
Re: LOGIC
No, No...
The same data on left and right. Only fsync is inverted between left and right.
This is the classical Audionote schematic.
We spoke here about this, and the nor gates could be replaced by simple inverters without major change in the final result.
Nothing very original here : I/U by a resistor, gain with a common cathode and cathode follower for the output impedance...
ECC88 I think, if we consider the psu caps : 50V + 50V, then B+<100V.
Philippe
kkchunghk said:
No, No...
The same data on left and right. Only fsync is inverted between left and right.
This is the classical Audionote schematic.
We spoke here about this, and the nor gates could be replaced by simple inverters without major change in the final result.
Nothing very original here : I/U by a resistor, gain with a common cathode and cathode follower for the output impedance...
ECC88 I think, if we consider the psu caps : 50V + 50V, then B+<100V.
Philippe
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