I2S 16 vs. 24 bit as in PCM 1792 data sheet?

[capslock]

Any idea as to why the PCM 1792 has a default 24 bit I2S mode, but offers a 16 bit I2S mode as well? To the best of my knowledge, I2S is (in contrast to standard = Sony = right justified mode) MSB justified. This means a 16 bit signal fed to a 24 bit input receiver will simply set the 8 LSB to 0 which does not make any difference.

 

[mcs]

This means a 16 bit signal fed to a 24 bit input receiver will simply set the 8 LSB to 0 which does not make any difference.

But what if the 8 bits following the 16 data bits are not 0? Some of the Crystal A/D converters transmit data for a level meter after the data bits for instance.

Best regards,

Mikkel C. Simonsen

 

[rfbrw]

Any idea as to why the PCM 1792 has a default 24 bit I2S mode, but offers a 16 bit I2S mode as well? To the best of my knowledge, I2S is (in contrast to standard = Sony = right justified mode) MSB justified. This means a 16 bit signal fed to a 24 bit input receiver will simply set the 8 LSB to 0 which does not make any difference.

The only requirement I2S makes of the serial clock or bitclock is that it provides enough edges to load all the data into the input register. That means bitclock can be as low as 32Fs.

ray.

 

[capslock]

Looking at the timing diagrams on page 10 (I believe) of the 1792 data sheet, there seem to be enough bit clock frames. The option to exclude non-audio information in those bits below the 16th one might well be the explanation.

 

[rfbrw]

Possibly but not probably. The 16bit I2S option predates Crystal's signal level bits by at least a decade. 16bit I2S with a 1.4MHz bitclock will not work with a dac expecting 24bit I2S with a bitclock of 2.1MHz or 2.8MHz.

ray.