Hello,
OP amps constructors advice to remove the gnd and power plane below the inputs pins of such OP amps to figth stray capacitance. Sometimes they advice it just for the inverted pin and output pin only. Sometimes non inverted pin is from the party about that layers removal, sometimes not according litterature. The input traces has to be thins as well to reduce that stray capacitance and also short between the source and the load.
An illlustration is when the non inverting pin is tied to ground for a transimpedance configuration (I/V) where this time a width trace to ground is better adviced in order this time to figth stray inductance.
To finish the confusion they do not speak about the clearance width, how much around should be that clearance with soic and more little op amps around the inverted pin and the output of the feedback loop for instance ? Should there still some gnd for the current return below that feedback loop below thhat trace or should one make a clearance below all the op amp ic and the rF feedback R as well (sometimes advised) ? In this scenario the ground loop if the gnd layers is apart/outside from the back for instead a coplanar WG on the first layer, then anyway the ground loop area will be larger and this is not one wants with high speed signal and large band widths, no ? Even less for I/V task in the digital domain ?!
This rF cap so should be with such op amp be the nearest to the input inverted pin as possible, but does it no creating an antennna effect on the first signal layet as the trace this time is large (pads) and the pads + the resistor be it smd could be a stray capacitance source as well ?
All of that is not clear to me, if one has an idea, I appreciated it.
Thanks
OP amps constructors advice to remove the gnd and power plane below the inputs pins of such OP amps to figth stray capacitance. Sometimes they advice it just for the inverted pin and output pin only. Sometimes non inverted pin is from the party about that layers removal, sometimes not according litterature. The input traces has to be thins as well to reduce that stray capacitance and also short between the source and the load.
An illlustration is when the non inverting pin is tied to ground for a transimpedance configuration (I/V) where this time a width trace to ground is better adviced in order this time to figth stray inductance.
To finish the confusion they do not speak about the clearance width, how much around should be that clearance with soic and more little op amps around the inverted pin and the output of the feedback loop for instance ? Should there still some gnd for the current return below that feedback loop below thhat trace or should one make a clearance below all the op amp ic and the rF feedback R as well (sometimes advised) ? In this scenario the ground loop if the gnd layers is apart/outside from the back for instead a coplanar WG on the first layer, then anyway the ground loop area will be larger and this is not one wants with high speed signal and large band widths, no ? Even less for I/V task in the digital domain ?!
This rF cap so should be with such op amp be the nearest to the input inverted pin as possible, but does it no creating an antennna effect on the first signal layet as the trace this time is large (pads) and the pads + the resistor be it smd could be a stray capacitance source as well ?
All of that is not clear to me, if one has an idea, I appreciated it.
Thanks
This has a good explanation.
https://www.analog.com/en/resources/technical-articles/layout-for-precision-op-amps.html
Another reference:
https://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241
https://www.analog.com/en/resources/technical-articles/layout-for-precision-op-amps.html
Another reference:
https://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241
Some say 5 mm clearance between the pin is needed ?
guard rings is a nigthmare with kickad... impossible to remove the soldermask or the guard ring traces : can not be managed like it was a simple pad !
(guards rings needto have the copper exposed to air or of course to be enabled with solder... the inkh layer of the silkscreen breaks that ring guard behavior...
guard rings is a nigthmare with kickad... impossible to remove the soldermask or the guard ring traces : can not be managed like it was a simple pad !
(guards rings needto have the copper exposed to air or of course to be enabled with solder... the inkh layer of the silkscreen breaks that ring guard behavior...
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According to you better to biass it a gnd level with the non inverting input to ground or better to biass it at op amp voltage level taking for instance from the positive voltage pin ?
Below soic size I think it becomes almost impossible to guard ring cause the little size of the ic and pins spacing... wanted to try the opa856 !
Below soic size I think it becomes almost impossible to guard ring cause the little size of the ic and pins spacing... wanted to try the opa856 !