Help me make sense of this ESS schematic

[mrjayviper]

This is what's written on the datasheet.

Paralleling DAC outputs as shown in Figure 1 is a technique used to further improve DNR and SNR performance. The ES9038PRO has a low output impedance (typ. 202ohm) and paralleling DAC outputs will further reduce the output impedance. Paralleling 4 channels as shown in Figure 1 will result in a 50ohm output impedance. Paralleling 8 channels will result in 25ohm. Many op amps used for the I/V stage (U1 and U3) to drive such a low impedance will have difficulty maintaining low THD and linearity. For the ES9038PRO, it is recommended to parallel DAC outputs after the output of U2 and use a set of op amps (U1, U2, U3) for all 8 channels.

If the design uses 2 ES9038pro chips which is the most I've seen in commercial designs, does it mean a balanced output would have 3 opamps (per + or - channel) between the DAC chip and the XLR connector? (so 12 opamps minimum for R+, R-, L+ and L- channels)

Thanks