Hello
I have just finished a cd player.
I have made it with a cdrom drive (asus 520), and I reclock the drive and the Dac with à low jitter clock from Guido.
I join the diagram and some timings.
As I have only two traces at my oscillo, all the timings where taken with Mclk. This permit to align them to have three or more traces synchronized.
You will find in the yellow circle the margin of + and - 10 ns approx. in which Fsync can move, and LL and LR will be allways sampled by the same clock pulse (second clock pulse on the diagram), then jitter = clok jitter + flip flop jitter = few jitter (I hope).
This permit to not have a perfect spdif link (with the condition to not create more than 10 ns jitter!)
This is possible because the cd drive and the dac are clocked by the same oscillator.
The sound of the cd seems quite good, the I/U is a D1 from Nelson Pass.
I will detail the analog part later...
Tell me what you think of this digital part and if my concept is reliable.
regards
Philippe
I have just finished a cd player.
I have made it with a cdrom drive (asus 520), and I reclock the drive and the Dac with à low jitter clock from Guido.
I join the diagram and some timings.
As I have only two traces at my oscillo, all the timings where taken with Mclk. This permit to align them to have three or more traces synchronized.
You will find in the yellow circle the margin of + and - 10 ns approx. in which Fsync can move, and LL and LR will be allways sampled by the same clock pulse (second clock pulse on the diagram), then jitter = clok jitter + flip flop jitter = few jitter (I hope).
This permit to not have a perfect spdif link (with the condition to not create more than 10 ns jitter!)
This is possible because the cd drive and the dac are clocked by the same oscillator.
The sound of the cd seems quite good, the I/U is a D1 from Nelson Pass.
I will detail the analog part later...
Tell me what you think of this digital part and if my concept is reliable.
regards
Philippe
Attachments
Hi,
If you are afraid of the timing not matching, you could have a look at an asynchronous fifo.
Start the filling with 8414 clock and then start the reading when the half-full flag is triggered with a (divided i guess) G.Tent clock.
Still reclock after this with a ff.
Works fine for me (with I2S), i dont have a nice scope to measure things 😀
If you are afraid of the timing not matching, you could have a look at an asynchronous fifo.
Start the filling with 8414 clock and then start the reading when the half-full flag is triggered with a (divided i guess) G.Tent clock.
Still reclock after this with a ff.
Works fine for me (with I2S), i dont have a nice scope to measure things 😀
Hi
With the setting that I have made, I will begin to have synchro problems when fsync is shifted of + or - 10 ns. I never saw that in all the tries I have made. I dont think that this could happen. Or if it happens, others errors will come, that will not be able to be corrected.
And if a synchro problem comes, the only effect is to shift LL or LR of a clock period, which is 30 ns. This is enormous jitter, but is theoricaly (and practicaly) impossible.
Philippe
With the setting that I have made, I will begin to have synchro problems when fsync is shifted of + or - 10 ns. I never saw that in all the tries I have made. I dont think that this could happen. Or if it happens, others errors will come, that will not be able to be corrected.
And if a synchro problem comes, the only effect is to shift LL or LR of a clock period, which is 30 ns. This is enormous jitter, but is theoricaly (and practicaly) impossible.
Philippe
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