Hi, I'd like to discuss about digital source switching.
It came up a couple of times, I read the threads, but I'd like to wake up the subject.
I hope people like Guido and Jocko will comment ^^
Say I have a bunch of i2s, dsd, spdif... signals I want to feed into the inputs of the ESS Sabre DAC. When I mean a bunch, it's not just switching between two sources... It goes really fast, for example: aes3, aes3id, spdif, optical, DSD, ADAT (with source selection between the 4 i2s data lines), USB, TDIF: We already have 11 sources! Ok it's a bit extreme but let's just say I'd like to be able to do it...
Remember this data will be output by a comparator at CMOS level. Fast, low jitter comparators don't like any capacitive load and that's a major issue. Plus remember capacitive load will decrease the bandwith, thus increase jitter (unless you were spitting HF crap, but that shouldn't be the case).
What can we do then?
Electromechanical:
- Manual switches, Manual RF switches: out of question for obvious reasons.
- Relays, small RF relays
Active:
- Tristate bus
- 74 series MUX
- OPA4872/AD8174/AD8184
We may use SPDT RF relays and chain them hierachically to add inputs, or we may use SPST as a tristate bus.
Pros: No active
Cons: More complex command, higher capacitance. More expensive, and consider I'd only use very cheap RF board mount relays.
Tristate bus:
Use logic buffers, analog buffers with EN, or comparator's EN input (if any).
Best would be to use the comparator's EN input as you don't add useless circuitry, BUT on that tristate bus we'll have both stray capacitance (and to connect all input... That will make quite a large one), and added capacitance of each output. These will heavily filter the signal, and more importantly mess up the comparator.
Analog buffers have their own problems like offset etc... Fast ones often use current feedback so we have useless G=+2.
Logic buffers: we still have quite a lot of stray capacitance, maybe using mux instead of ANDs will yeld better result?
74 series tristate MUX: these logic families aren't especially fast... But they are cheap! Cascade them to get as many inputs as desired.
OPA4872 or AD8174 or AD8184 are something slightly different: they are high frequency analog muxes. Only the 8184 has a gain of 1, two others have a gain of 2 - and a PS of 6.5, so you'll have to divide the signal by two before this chip's input, otherwise you'll be clipping the output - and it will need some time to recover, and that time won't even be symmetrical. That's not that important because a series/parallel termination will divide by 2, so you trade something for something else, but distance from the comparator output to mux input is too short to really need impedance matching. It also needs bipolar supply, not a real problem in my case. But there must be some other problems with this solution I don't clearly see... And you're back in a linear domain, not on/off logic, gain may not be exact and flat, so you're adding distortion to a perfectly clean signal output from a comparator... And adding another comparator doesn't seem like the best option to me. I wouldn't either rely on these to transmit the low level signal recovered from say SPDIF, plus my own spdif receiver interface needs its own comparator (a kind of strange design, with kind of a servo, that seems to work really well, but I won't tell more until I can fully spec the design).
Tell me what you think 🙂
Thanks
Nicolas
It came up a couple of times, I read the threads, but I'd like to wake up the subject.
I hope people like Guido and Jocko will comment ^^
Say I have a bunch of i2s, dsd, spdif... signals I want to feed into the inputs of the ESS Sabre DAC. When I mean a bunch, it's not just switching between two sources... It goes really fast, for example: aes3, aes3id, spdif, optical, DSD, ADAT (with source selection between the 4 i2s data lines), USB, TDIF: We already have 11 sources! Ok it's a bit extreme but let's just say I'd like to be able to do it...
Remember this data will be output by a comparator at CMOS level. Fast, low jitter comparators don't like any capacitive load and that's a major issue. Plus remember capacitive load will decrease the bandwith, thus increase jitter (unless you were spitting HF crap, but that shouldn't be the case).
What can we do then?
Electromechanical:
- Manual switches, Manual RF switches: out of question for obvious reasons.
- Relays, small RF relays
Active:
- Tristate bus
- 74 series MUX
- OPA4872/AD8174/AD8184
We may use SPDT RF relays and chain them hierachically to add inputs, or we may use SPST as a tristate bus.
Pros: No active
Cons: More complex command, higher capacitance. More expensive, and consider I'd only use very cheap RF board mount relays.
Tristate bus:
Use logic buffers, analog buffers with EN, or comparator's EN input (if any).
Best would be to use the comparator's EN input as you don't add useless circuitry, BUT on that tristate bus we'll have both stray capacitance (and to connect all input... That will make quite a large one), and added capacitance of each output. These will heavily filter the signal, and more importantly mess up the comparator.
Analog buffers have their own problems like offset etc... Fast ones often use current feedback so we have useless G=+2.
Logic buffers: we still have quite a lot of stray capacitance, maybe using mux instead of ANDs will yeld better result?
74 series tristate MUX: these logic families aren't especially fast... But they are cheap! Cascade them to get as many inputs as desired.
OPA4872 or AD8174 or AD8184 are something slightly different: they are high frequency analog muxes. Only the 8184 has a gain of 1, two others have a gain of 2 - and a PS of 6.5, so you'll have to divide the signal by two before this chip's input, otherwise you'll be clipping the output - and it will need some time to recover, and that time won't even be symmetrical. That's not that important because a series/parallel termination will divide by 2, so you trade something for something else, but distance from the comparator output to mux input is too short to really need impedance matching. It also needs bipolar supply, not a real problem in my case. But there must be some other problems with this solution I don't clearly see... And you're back in a linear domain, not on/off logic, gain may not be exact and flat, so you're adding distortion to a perfectly clean signal output from a comparator... And adding another comparator doesn't seem like the best option to me. I wouldn't either rely on these to transmit the low level signal recovered from say SPDIF, plus my own spdif receiver interface needs its own comparator (a kind of strange design, with kind of a servo, that seems to work really well, but I won't tell more until I can fully spec the design).
Tell me what you think 🙂
Thanks
Nicolas
i would recomend small cpld device since it have all pins you need and more (in/out) small delays, fit output capasitance, no external components (except receivers and dac). use some good software to assemble device (witch can configure voltage... or just set capacitance and compiler will take care)
Ps. tried google for dac datasheet and all i found was fancy words and couple graps that show how great snr and low distortion that dac have
where i can found real datasheet?
Ps. tried google for dac datasheet and all i found was fancy words and couple graps that show how great snr and low distortion that dac have
where i can found real datasheet?
The Datasheet is submitted to NDA. You will find white papers on ESS's website talking about the technology inside. It really sounds great, but if you consider all the surrounding components/voltage regulation/IV etc you end up with a very high cost compared to top of the line TI/BB components. Wether it is worth is questionable. But sound is really great!
It sounds different to others, I must admit. Something more smooth but more controlled. It really shines in low frequencies, where it's ultra low jitter and distortion allows for a far better perception of space. And if you listen to music with low sounds and infrabass, you'll be amazed how clean and precise these come. And that's something that other converters, despite their good measurements, don't rival to my ears - and I'm a sound engineer, my main job is not making sound devices, but to record music and sound effects.
For the switching question, you may be right. It is really hard to find any jitter information on logic gates, and VHC isn't even that fast. This DAC should stand down to 1ns rise/fall times. I'll probably use de 3-5ns comparator, VHC is up to 10ns, sometimes 8ns, sometimes 6... But even Potato semiconductors, who make the fastest logic chips in the world, spec 100pS Jitter!
Do you think of any fast/low jitter CPLD?
EDIT:
To feed some info to the thread:
74xxx153, dual 4-to-1 selector/multiplexer
Fairchild:
AC family, VCC=3V3, Cl=50pF, TA25°C tpl 2.5-9.5-15 ns, tphl 3-8.5-14.5 ns
VHC family, VCC=3V3, Cl=50pF, TA25°C tplh=tphl 10.2 typ 15.4 max ns.
BUT
VHC family, VCC=3V3, Cl=15pF, TA25°C tplh=tphl 7.7 typ 11.9 max ns.
So, if you can keep the Cl very low, VHC clearly wins. AC family has something we won't like for our applications: tplh and tphl are not the same. VHC should be more balanced.
Now, that doesn't says much about noise, 1/F, and jitter induced...
It sounds different to others, I must admit. Something more smooth but more controlled. It really shines in low frequencies, where it's ultra low jitter and distortion allows for a far better perception of space. And if you listen to music with low sounds and infrabass, you'll be amazed how clean and precise these come. And that's something that other converters, despite their good measurements, don't rival to my ears - and I'm a sound engineer, my main job is not making sound devices, but to record music and sound effects.
For the switching question, you may be right. It is really hard to find any jitter information on logic gates, and VHC isn't even that fast. This DAC should stand down to 1ns rise/fall times. I'll probably use de 3-5ns comparator, VHC is up to 10ns, sometimes 8ns, sometimes 6... But even Potato semiconductors, who make the fastest logic chips in the world, spec 100pS Jitter!
Do you think of any fast/low jitter CPLD?
EDIT:
To feed some info to the thread:
74xxx153, dual 4-to-1 selector/multiplexer
Fairchild:
AC family, VCC=3V3, Cl=50pF, TA25°C tpl 2.5-9.5-15 ns, tphl 3-8.5-14.5 ns
VHC family, VCC=3V3, Cl=50pF, TA25°C tplh=tphl 10.2 typ 15.4 max ns.
BUT
VHC family, VCC=3V3, Cl=15pF, TA25°C tplh=tphl 7.7 typ 11.9 max ns.
So, if you can keep the Cl very low, VHC clearly wins. AC family has something we won't like for our applications: tplh and tphl are not the same. VHC should be more balanced.
Now, that doesn't says much about noise, 1/F, and jitter induced...
Last edited:
The linear chips I talked about can handle down to 1.2ns tpd. But we don't know much about wether tphl/tplh are the same, the offset, the noise... And I can't predict wether it will yeld any better results.
OTOH, I searched for CPLDs and found 400Mhz ones with 2.5ns tpd...
This is damn impressive and probably the most effective way to route these signals!
OTOH, I searched for CPLDs and found 400Mhz ones with 2.5ns tpd...
This is damn impressive and probably the most effective way to route these signals!
Last edited:
Something like this, would been nice...with BNC, and more inputs...
SPDIF 4x1 Digital Audio Switcher
Arne K
SPDIF 4x1 Digital Audio Switcher
Arne K
NeoY2K,
That would be a very nice project. Wish I had the knowledge to contribute, but at the other diy site, there is a similar project: IC: DIY spdif switcher - Head-Fi: Covering Headphones, Earphones and Portable Audio
That would be a very nice project. Wish I had the knowledge to contribute, but at the other diy site, there is a similar project: IC: DIY spdif switcher - Head-Fi: Covering Headphones, Earphones and Portable Audio
In my own project i am using fpga to generate mclk, bclk,i2c clock, i2c data, L/R and audio data (wolfson's stereo dac).
When using programmable device like fpga and considering jitter It's not how fast rise/fall times you have. it's precision that make difference. In theory if you have constant rise/fall times you have no jitter (you can always sync signals) but in real life...
just noticed why do you need comparator at CMOS level in digital system? Are you making standalone source witching device?
Use single chip to control dac mclk audio data & clk, pdif interface and control intrface to control jittter.
74 series or similiar devices can't drive dac alone multiple devices causes jitter. Improving that you have to step to dark site.
When using programmable device like fpga and considering jitter It's not how fast rise/fall times you have. it's precision that make difference. In theory if you have constant rise/fall times you have no jitter (you can always sync signals) but in real life...
just noticed why do you need comparator at CMOS level in digital system? Are you making standalone source witching device?
Use single chip to control dac mclk audio data & clk, pdif interface and control intrface to control jittter.
74 series or similiar devices can't drive dac alone multiple devices causes jitter. Improving that you have to step to dark site.
Hi Nicolas,
I guess I am a little confused. If you want to switch digital sources, why not use a straight MUX which is designed to switch digital sources? An 8:1 MUX is readily available in many variants, and these can be easily extended to any size desired. There is no need to mess around with tristate outputs. Fast CMOS or even old fashioned 74150 (16:1) are still readily available.
I would avoid CPLD for this sort of thing like the plague. These aren't very efficient for logic like a MUX, and the added circuitry inside which is needed for flexibility will add noise, jitter, and capacitance.
If you really want to go crazy, you could look at exotic high-speed stuff like GaAs MUX switches (often used in optical applications) but I suspect CMOS would work just fine.
Perhaps I misunderstood your requirements?
I guess I am a little confused. If you want to switch digital sources, why not use a straight MUX which is designed to switch digital sources? An 8:1 MUX is readily available in many variants, and these can be easily extended to any size desired. There is no need to mess around with tristate outputs. Fast CMOS or even old fashioned 74150 (16:1) are still readily available.
I would avoid CPLD for this sort of thing like the plague. These aren't very efficient for logic like a MUX, and the added circuitry inside which is needed for flexibility will add noise, jitter, and capacitance.
If you really want to go crazy, you could look at exotic high-speed stuff like GaAs MUX switches (often used in optical applications) but I suspect CMOS would work just fine.
Perhaps I misunderstood your requirements?
Thank you for your advices, and sorry for the late replies.
fzaad, thank you for sharing your experience with CPLD - I designed with some, but never in jitter-critical applications. Could you tell me/help me to pick a low jitter device? What should I be looking for?
Torrence: well, even VHC chips that seem the best (AC/ACT not symmetrical, even if they could go faster, and have higher tolerances) are old, max I can get is 4:1 so I have to use them in series or bus anyway. Complex PCB layout, vias in the RF signal path, etc...
I'm not sure CPLD has inherently more jitter - ok, it's a lot more complex, but it can adjust delay with a precision that is 40dB (at least) lower than just the VHC chips tolerance, so it means someone took care, somehow, to provide precise timing. And these devices are new, and are where research headed.
However, I have no definite answer about which technology to use. I'm more heading toward CPLD as it could handle all the routing (and maybe a bit of external signal processing etc).
fzaad, thank you for sharing your experience with CPLD - I designed with some, but never in jitter-critical applications. Could you tell me/help me to pick a low jitter device? What should I be looking for?
Torrence: well, even VHC chips that seem the best (AC/ACT not symmetrical, even if they could go faster, and have higher tolerances) are old, max I can get is 4:1 so I have to use them in series or bus anyway. Complex PCB layout, vias in the RF signal path, etc...
I'm not sure CPLD has inherently more jitter - ok, it's a lot more complex, but it can adjust delay with a precision that is 40dB (at least) lower than just the VHC chips tolerance, so it means someone took care, somehow, to provide precise timing. And these devices are new, and are where research headed.
However, I have no definite answer about which technology to use. I'm more heading toward CPLD as it could handle all the routing (and maybe a bit of external signal processing etc).
The low tolerance of the general CMOS logic's propagation delay is usually not specified as variations due to process, voltage or temperature. I would expect that it is due in most part to process, for a better yield. And that doesn't really affect jitter in a given application.
If in doubt, you can always use a FET switch that is equivalent of a resistor. The specified prop. delay is in the neighborhood of 150ps with a few pf of capacitance to GND. The down side is that it is a passive passing device with a finite on-state resistance ranging from a few ohms to a few tens of ohms. People who are paranoid about perfect impedance matching may find them difficult to deal with.
If in doubt, you can always use a FET switch that is equivalent of a resistor. The specified prop. delay is in the neighborhood of 150ps with a few pf of capacitance to GND. The down side is that it is a passive passing device with a finite on-state resistance ranging from a few ohms to a few tens of ohms. People who are paranoid about perfect impedance matching may find them difficult to deal with.
I'm about to do exactly the same thing: a switch between DSD, I2S and SPDIF with multiple input for all of these to the ESS DAC.
I will also be using a CPLD device. The Altera Max II (micro development kit from terasic).
propagation delay is not really a problem as long as all the lines are the same length. You can optimize for this if you like.
Well, about jitter: who cares...? The DAC is asynchronous, and is known for it's extreme jitter rejection.
I'm guessing that CPLD will not do worse in this regard that an analog switch, analog HF mux, relay, or logics composed of a few logic chips... And you can do much more fun stuff with it, like detecting the sampling frequency 😉
I will also be using a CPLD device. The Altera Max II (micro development kit from terasic).
propagation delay is not really a problem as long as all the lines are the same length. You can optimize for this if you like.
Well, about jitter: who cares...? The DAC is asynchronous, and is known for it's extreme jitter rejection.
I'm guessing that CPLD will not do worse in this regard that an analog switch, analog HF mux, relay, or logics composed of a few logic chips... And you can do much more fun stuff with it, like detecting the sampling frequency 😉
Yep... Hard to choose in fact.
4real: well, in fact, there is a read only register inside the ESS that will tell you the sample rate xD save some time xD
4real: well, in fact, there is a read only register inside the ESS that will tell you the sample rate xD save some time xD
I do not have the datasheet, so I don't know about the registers 🙁
It would be intersting to read them, saves me a lot of time😉
- Status
- Not open for further replies.