Hi ,
sorry I know its a bit offtopic but I have a question about isolation transformers (DC/DC 2w)
We have a FPGA board that needs a clock..of course we are feeding the clock using a low noise LDO
However one of our engineers is proposing to add a DC/DC isolation transformer before the clock to reduce further the noise.
Is that a valid approach ?
sorry I know its a bit offtopic but I have a question about isolation transformers (DC/DC 2w)
We have a FPGA board that needs a clock..of course we are feeding the clock using a low noise LDO
However one of our engineers is proposing to add a DC/DC isolation transformer before the clock to reduce further the noise.
Is that a valid approach ?
Your term 'DC/DC isolation transformer' is a little confusing. Does it just mean 'a pulse transformer' ? In which case yes its a good idea, it helps to avoid groundplane noise being coupled into the clock signal. Essentially, with a transformer the clock can be sent from the oscillator in balanced form - the transformer at the FPGA converts it back to single ended.
However should your term actually mean 'isolated DC/DC converter', its not a good idea as most such modules are noisy. They're the last thing you'll want on your board if noise reduction is the aim.
However should your term actually mean 'isolated DC/DC converter', its not a good idea as most such modules are noisy. They're the last thing you'll want on your board if noise reduction is the aim.
since transformers don't work at DC the term DC/DC 2W refers to power conversion SMPS then the added "transformer" term refers to galvanic isolation.
can it help? sure, it can also make things worse. DC Isolation implies corrupt grounding so differential outputs with a carefully selected low noise SMPS can work with proper PCB layouts etc.
can it help? sure, it can also make things worse. DC Isolation implies corrupt grounding so differential outputs with a carefully selected low noise SMPS can work with proper PCB layouts etc.
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not sure what the target ripple and noise spec is, why not call that vendors app engineer ?they can suggest the best solution for your needs> they do have some very low noise stuff. bread boarding is suggested with the clock circuitry then look at the clock spectrum.
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Powering a clock from a local SMPS doesn't look to me to be a good idea. The spec says 14mV output ripple but doesn't give a frequency.
there are good ones, ive designed one to bias a VCO varactor diode before, in a STB TV tuner!
is that one good, IDK I didn't study it. he needs to leave it up to the responsible engineer, its not just the converter. LDO, isolated grounds, and diff outputs all working together
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Yes - if low noise is the aim then 'better the devil you know' says to me design it yourself so you'll have some idea what its emissions are going to be. A varactor bias supply will be an extremely low power one, far lower than this one (1W) being suggested here. Lower power means less noise, in general.
indeed that's why I suggested he call an app engineer that knows their full product line.
the approach can be worked, but not at the single component level.
the approach can be worked, but not at the single component level.
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If the engineer's original aim is to have an isolated ground so he can couple the clock in to the FPGA without worrying about groundplane noise, I think the medicine's probably worse than the disease. Better to use an isolation transformer (bal-SE at the FPGA) for just the clock signal I think.
I've been out of touch with FPGAs for some time but last time I looked they had PLLs on-chip to multiply up external clocks. So they'd not need such high freqs externally.
The FPGA has PLLs however they PLLs have high jitter.
We want to take the MCLK from a low jitter clock ..outside the FPGA
So my question was..do you think that DC/DC converter will offer additional benefits to an LDO (to power an external clock)
We want to take the MCLK from a low jitter clock ..outside the FPGA
So my question was..do you think that DC/DC converter will offer additional benefits to an LDO (to power an external clock)
FPGAs themselves have fairly high jitter (in my limited understanding) whether PLLs are used or not. So your engineer should not just focus on the jitter on the incoming clock but figure out what the output jitter is too.
If you need a high frequency clock, put it very close to the FPGA and use a low noise regulator. Wenzel has this suggestion for lowest noise - Finesse Voltage Regulator Noise! |
If you need a high frequency clock, put it very close to the FPGA and use a low noise regulator. Wenzel has this suggestion for lowest noise - Finesse Voltage Regulator Noise! |
if the DC converter offers lower ripple and noise including CM, than the FPGA ground / power, its possible, but it can be easy to mess it up too. unless the converter mention low noise I would keep looking. It might behoove you get a better handle on the actual power used. as usual breadboarding minimizes risk
that is problematic considering split power & gnd planes , ever hear of smb connectors?
I've heard of them, sure. Without more details its probably pointless to speculate what the best option is going to be. I can't see what an off-the-shelf DC/DC converter is going to bring to the party, other than grief.
I do believe they exist, does he have the right one, probably not
but a boost converter and small discrete linear Vreg can work to free up grounding without an needing a new external supply. spurs 50-60 dB down sure, 80-100 down then we might have a problem.
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So far I've only been speculating what problem is intended to be solved by adding in the DC/DC. OP - care to enlighten us what the engineer's rationale was?
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