Hi,
I am curious how to properly choose/setup rail voltage for my power amp. The Amplifier is in Class A, push pull, dual rail supply, final is complementaryMOSFET (IRFP240/9240 pairs).
What I know, the max output power should be satisfying both formulas below:
P = V^2 / R speaker, and
P = I^2 * R speaker
In class A, the I should be Iq to keep it always in Class A at desired wattage, and then calculating minimum V rms required, while V peak is about Vrms * 1.4.
Since the final is in Power Follower, then the gain is less than or equal to 1, so the previous stage should have higher rail voltage to create voltage swing as required without clipping.
Anyway, I found common schematic use much higher final stage supply rail than previous stage (LTP/VAS). Why should be so, as theoritically, the maximum output voltage is always below or equal to previous stage/VAS/LTP voltage (since gain <=1)?
Is there any benefit doing so, e.g. more liniearity?
And about Vgs maximum, will this also limit the maximum voltage swing (=power) that can be delivered in Power Follower design?
Thanks,
Ervin L
I am curious how to properly choose/setup rail voltage for my power amp. The Amplifier is in Class A, push pull, dual rail supply, final is complementaryMOSFET (IRFP240/9240 pairs).
What I know, the max output power should be satisfying both formulas below:
P = V^2 / R speaker, and
P = I^2 * R speaker
In class A, the I should be Iq to keep it always in Class A at desired wattage, and then calculating minimum V rms required, while V peak is about Vrms * 1.4.
Since the final is in Power Follower, then the gain is less than or equal to 1, so the previous stage should have higher rail voltage to create voltage swing as required without clipping.
Anyway, I found common schematic use much higher final stage supply rail than previous stage (LTP/VAS). Why should be so, as theoritically, the maximum output voltage is always below or equal to previous stage/VAS/LTP voltage (since gain <=1)?
Is there any benefit doing so, e.g. more liniearity?
And about Vgs maximum, will this also limit the maximum voltage swing (=power) that can be delivered in Power Follower design?
Thanks,
Ervin L
take one half of your push pull output stage.
A single mosFET with source connected to output via it's source resistor. Drain connected to +ve supply. The gate is connected to the output of the voltage amplifier. The output is connected to ground via an 8r0 load resistor.
Now add in your actual +ve supply voltage.
Assume a gate voltage = +ve supply voltage.
What is the voltage at the mosFET source?
What is the voltage at the 8r0 load?
What are the currents flowing through each of the connections around the FET?
If the gate voltage is raised to +ve plus 1V, then what effect does this have on all the voltages and currents around the FET?
At low output current the Vgs could be 4Vgs. At high output current the Vgs could be 7Vgs.
If you want the maximum output voltage to be nearly as high as the +ve supply voltage then the maximum voltage at the gate must be ~7V higher than the FET's source voltage.
That is another way of saying: If I want the maximum ClassA output for the minimum wasted heat in the output stage then the voltage amp should supply a peak to peak signal voltage that is 10Vpp to 15Vpp more than the sum of the dual polarity supply rails.
A word of caution.
ClassA output is current limited not power limited.
What is the maximum current that your speaker might demand?
Do you want the amplifier to stay in ClassA to meet every current demand of a speaker driven to it's maximum SPL? Most settle for much less than this and allow the amplifier to crossover to ClassAB for extreme transient currents.
A single mosFET with source connected to output via it's source resistor. Drain connected to +ve supply. The gate is connected to the output of the voltage amplifier. The output is connected to ground via an 8r0 load resistor.
Now add in your actual +ve supply voltage.
Assume a gate voltage = +ve supply voltage.
What is the voltage at the mosFET source?
What is the voltage at the 8r0 load?
What are the currents flowing through each of the connections around the FET?
If the gate voltage is raised to +ve plus 1V, then what effect does this have on all the voltages and currents around the FET?
At low output current the Vgs could be 4Vgs. At high output current the Vgs could be 7Vgs.
If you want the maximum output voltage to be nearly as high as the +ve supply voltage then the maximum voltage at the gate must be ~7V higher than the FET's source voltage.
That is another way of saying: If I want the maximum ClassA output for the minimum wasted heat in the output stage then the voltage amp should supply a peak to peak signal voltage that is 10Vpp to 15Vpp more than the sum of the dual polarity supply rails.
A word of caution.
ClassA output is current limited not power limited.
What is the maximum current that your speaker might demand?
Do you want the amplifier to stay in ClassA to meet every current demand of a speaker driven to it's maximum SPL? Most settle for much less than this and allow the amplifier to crossover to ClassAB for extreme transient currents.
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